NV3 memory mapping

Understanding the memory mapping of the NV3 is critical for understanding its overall operation.

The memory mapping architecture is implemented internally by the NV3 on-die memory controller and exposed to the user via the configuration register interface of the Peripheral Connect Interface (PCI) bus and its siblings and successors, such as AGP (or in later models, PCIe). Two of the maximum fsix base address registers are exposed using this mechanism, BAR0 and BAR1; BAR2 is claimed to exist by some sources, including envytools, but doesn't seem to actually exist. BAR0 contains a gigantic slab (16MB) of MMIO containing all registers, and BAR1, also 16MB, contains both a copy of the current framebuffer (or all of VRAM?) for dumb framebuffer use, and, at 0xC00000, instance memory mapped as it is intended to be addressed.

Memory mapping

BAR0 (MMIO)

NV3 BAR0 mapping

Start	End	Name	Purpose
0x0	0xFFF	PMC	Control GPU subsystems, boot-time config info & global GPU interrupt status and control
0x1000	0x17FF	PBUS	PCI/AGP electrical configuration, memory controller, DMA controller
0x1800	0x18FF	PCI config space mirror	PCI configuration for exposing the GPU to the rest of the machine, including vendor and device IDs, BARs for MMIO and VRAM mapping by the OS and various other characteristics. Technically a part of PBUS [1]
0x2000	0x3FFF	PFIFO	FIFO buffer using Gray code indexing; allows objects to be submitted in one of two caches (the one-entry CACHE0 used for software method injection and the 32 or 64 (NV3T)-deep CACHE1), storing them in a queue their methods can be executed; supports up to 8 DMA channels for object submission with 8 subchannels each, "context switching" is needed (see RAMFC) to change which DMA channel is selected.
0x4000	0x5FFF	PRM	Legacy Sound Blaster/MPU-401 support on MS-DOS
0x6000	0x6FFF	PRAM	NV1 leftover that controlled the amount of RAM used for GPU control structures, unused.
0x7000	0x7FFF	PRMIO	Real Mode I/O. In practice only used for the Real Mode Access (RMA) feature (at MMIO 0x7100) that allows reading and writing, to the GPU's MMIO space from real-mode (by using the x86 in/out instructions on legacy SVGA ports) without mapping any of the BARs; this is used by the VBIOSS to talk to the main part of the GPU.
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC
0x0	0xFFF	PMC

Notes

^ Repeated from 0x1900-0x19FF due to incomplete address decoding