NV3 PMC

PMC (Master Control), in Nvidia-based GPUs, is the subsystem that controls all of the other subsystems and, furthermore, controls interrupts for the entire GPU. The NV3 version is fairly basic: it stores some manufacture-time configuration info, allows disabling and enabling interrupts, reading and writing interrupt status and enabling and disabling most other subsystems of the GPU. Certain subsystems, such as PTIMER, cannot be disabled as they are critical to GPU operation; disabling all subsystems on a running system with the Nvidia drivers installed will typically crash the GPU and probably the computer it is running under too. Additionally, disabling interrupts does not seem to work as intended (see Hardware errata).

Notifications are an entirely different hardware subsystem that is much more complex and has a partially overlapping function with interrupts.

Registers

PMC_BOOT_0

• MMIO offset: 0x0
• Available in: NV1+
• Read/write

Holds part of the manufacture-time configuration information (the rest is held in the Straps for OEM-level configuration, and PFB_BOOT_0 for more manufacture-time configuration). Presumably this information was encoded into the die by Nvidia and/or SGS-Thomson in the factory, possibly via focused ion beam (FIB) chip modification techniques.

PMC_BOOT_0 register bits

Bit range (high:low)	Name	Purpose	Values
3:0	FIB_REVISION	Focused ion beam chip modification revision. Presumably for modifying the chip to fix bugs after the die is manufactured	0 = revision 0 1 = revision 1 2 = revision 2 (NV3T, stepping A03/A04)
7:4	MASK_REVISION	Revision of the silicon die.	0 = revision A, RIVA 128 prototype (design finished late January 1997; tapeout March; first prototypes start of April 1997) 1 = revision B, RIVA 128 (already in production by week 33 of 1997) 2 = revision C, RIVA 128 ZX
15:8	IMPLEMENTATION	Variation of the architecture. This is actually an unused leftover from the NV1 era, where different versions were sold with slightly different functionality (in the case of the NV1, these were the NV0, NV1 with 32-bit DRAM, NV1 with 32-bit VRAM, and an NV1 with a "Picasso" 128-bit DAC), as well as scrapped plans for an audio-less STG-3000 later on.	0 = NV3
23:16	ARCHITECTURE	The version of the NV architecture.	0 = NV0 (never intended to use silicon?) 1 = NV1 2 = NV2 (cancelled) 3 = NV3 In practice only the value 3 will ever be used on NV3.
27:24	MANUFACTURER	Another NV1 remnant, from when the NV1 could either be branded as the SGS-Thomson STG-2000 (1, MANUFACTURER_SGS) or the Nvidia NV1 (0, MANUFACTURER_NV.	0 = Nvidia
31:28	FOUNDRY	The foundry partner that manufactured the GPU.	0 = SGS-Thomson/STMicroelectronics 1 = Helios 2 = TSMC (NV3T / Riva 128 ZX only)

It is not clear what company the name "Helios" refers to. There is a company called Helios Semiconductor, founded in Taiwan on 12 March 1997. However, it is an IC design company focusing on low-end DSPs, LCD controllers, codec decoders, speech synthesis devices (and various other speech-related devices) and MIDI controllers; in the past (~2001) they also made SoCs for PDAs (the heritage of which is still in their modern chips, as they use proprietary 8/16-bit RISC CPU architectures originally designed for this purpose in many of their products), which were strangely branded as "cyber neural processors". It seems extremely unlikely that this company ever owned or operated a silicon fab, and it was founded just weeks before the NV3 taped out and manufacturing it would have been logistically impossible (let alone any earlier Nvidia chips). Additionally, Helios' initial capitalisation of $2.5 million is an implausibly low amount for a fab company, even in 1997. It is possibly an earlier name for a known chip company. There is another company that fabricated batteries called Helios, but it was founded long after the RIVA 128 was discontinued; it's possible Nvidia intended to use Helios's parts but this is still extremely unlikely, since the company was barely founded, obscure, and had very few employees, and even then wouldn't be justified as a "foundry". The NV2 is set to have a PMC_BOOT_0 value of 0x10020400, implying that it would have been manufactured by this mysterious company.

What Nvidia appear to have been the intended values for various NV3-based chips is listed below. The value hardcoded in the Nvidia drivers for NV3T-based cards is hardcoded to one that implies a TSMC-manufactured card, although presumably, STMicro-manufactured NV3T chips (which are confirmed to exist) have bits 31 through 27 as zero rather than two (so e.g. 0x20030120, used as the value for stepping A01 NV3Tc hips, would become 0x00030120). Only the revision bits are checked (it has to be 0x20 or higher) when determining if "RIVA 128" or "RIVA 128 ZX" should be printed on the sign-on screen in NV3T-compatible versions of the NV3 video BIOS code.

PMC_BOOT_0 value table

GPU revision	PMC_BOOT_0 value
NV3 revision A	0x00030100
NV3 revision B	0x00030110
NV3T revision A01 (NV3 revision C)	0x20030120
NV3T revision A02 (NV3 revision C)	0x20030121
NV3T revision A03/A04 (NV3 revision C)	0x20030122

PMC_ENABLE_0

• MMIO offset: 0x200
• Available in: NV1+
• Read/write

Determines which GPU subsystems are enabled and available for use. It is currently unclear what reading and writing to the MMIO register space of a disabled GPU subsystem will actually do. The GPU subsystem certainly ceases to function, since disabling all GPU subsystems while the drivers are running causes an immediate crash and display corruption (a chunk of the leftmost part of the screen is repeated numerous times across the entire screen, almost as if the RAMDAC is "spinning" waiting for new data to come in that never does).

Certain subsystems, such as PTIMER, PRAMDAC, and PBUS (the internal GPU bus), that are critical for system operation, cannot be disabled (PEXTDEV, the VBIOS mirror at 0x110000, RMA, and the PCI configuration space mirror at 0x1800 also cannot be turned off). Strangely, PAUDIO, removed after the revision A of the NV3, is still listed in this register. The effect of disabling this nonexistent subsystem is unknown. Additionally, the memory mapping of the GPU cannot be disabled via this mechanism; while it could be turned off by using the PCI configuration registers, the effects of this would be of questionable utility as the chip would basically become a silicon doorstop.

In all cases, a 1 for a particular bit enables the subsystem, while a zero disables it. This register, like many in the NV3 architecture, is structured so that, when the registers' value is interpreted as a hexadecimal number, each individual number represents one part of the register, and the number can be treated as a binary number (only 1 and 0 are relevant). This basically means that only eight settings are toggleable (as all Nvidia registers are 32-bit in size, regardless of how much of those are significant), and the settings toggled by the register are one nybble (four bits) apart.

Bits of the PMC_ENABLE register

Bit range (high:low)	Purpose
0	Enables or disables PAUDIO, which only truly exists on Revision A cards.
4	Enables or disables the Mediaport, which for some reason is called PMEDIA here and PME literally everywhere else.
8	Enables or disables PFIFO, the FIFO used for object submission. Critical for graphics operation.
12	Enables or disables PGRAPH, the graphics engine. Critical for graphics operation.
16	Enables or disables PPMI (Performance Measurement and Instrumentation? Performance Monitoring and Instrumentation?), an internal subsystem with no exposed registers that allowed Nvidia engineers to debug the GPU via the "NvWatch" software in debug compiled drivers.
20	Enables or disables PFB, the interface to the framebuffer and VRAM. Critical for graphics operation.
24	Enables or disables PCRTC, the CRT controller used for controlling the display and legacy VGA opeations. Critical for graphics operation.
28	Enables or disables PVIDEO, the video overlay managers.

PMC_INTR_EN_0

• MMIO offset: 0x140
• Available in: NV1+
• Read/write

Controls if interrupts are enabled chip-wide via bits 1:0 (INTR_EN_0_INTA). Does NOT affect notifiers!

PMC_INTR_EN_0 bits 1:0 value table (INTR_EN_0_INTA)

Value	Meaning
0 (DISABLED)	No interrupts are allowed.
1 (HARDWARE)	Hardware interrupts are enabled - hardware interrupts are generated by the GPU during normal operation, such as PGRAPH's VBLANK interrupt generated at every vertical blank)
2 (SOFTWARE)	Software interrupts are enabled (when software writes directly to the NV3 PMC#PMC_INTR_0 register)
3 (1 OR 2)	Both hardware and software interrupts are enabled.

PMC_INTR_READ

• MMIO offset: 0x160

Reflects the status of the INTA line for interrupt assertion into the hardware. If bit 0 is one, the INTA line is reading high, and if bit 0 is high, the INTA line is reading low. Presumably the value is disregarded if the value of PMC_INTR_EN_0 disables hardware (or software? since presumably another part of the system would be asserting this line) interrupts.

PMC_INTR_0

• MMIO offset: 0x100
• Available in: NV1+
• Read/write

Holds the status of pending interrupts for various subsystems. This register only lets you find out an interrupt is actually pending for a particular subsystem (indicated by the bit for this subsystem being one); further information on exactly which interrupt(s) are pending needs to be done by reading the requisite subsystem's interrupt status register. The interrupt also has to be enabled via the subsystem you are wishing to query's interrupt enable register; this is done by ANDing the interrupt enable and status registers together. If the result of this operation is non-zero, the interrupt is allowed, with one special case that will be explained below. There are also a few separate interrupt enable registers that are not covered by this.

PMC_INTR_0

Bit	Subsystem for which interrupts are pending	Notes
0	PAUDIO
4	Mediaport
8	PFIFO
12	PGRAPH (PGRAPH_0)	The check for if interrupts are allowed to be processed from PGRAPH_0 is actually nv3->pgraph.interrupt_status_0 & ~(1 << 8) && nv3->pgraph.interrupt_enable_0 & ~(1 << 8), rather than the usual interrupt enable register for subsystem AND interrupt status register for subsystem, since PFB (bit 24) uses PGRAPH's interrupt enable and status register.
13	PGRAPH (PGRAPH_1)	Nvidia ran out of interrupts in PGRAPH's interrupt status register, so they had to make a second one. There is a third one for the DMA engine not covered by PMC_INTR_0, which is mostly used in 3D rendering.
16	PVIDEO
20	PTIMER
24	PFB	Uses PGRAPH's interrupt enable and status registers for querying which interrupts are available and firing them (checked via nv3->pgraph.interrupt_status_0 & (1 << 8) && nv3->pgraph.interrupt_enable_0 & (1 << 8))
28	PBUS
31	Software	Used for software (usually driver)-initiated interrupts

This register, like many in the NV3 architecture, is structured so that, when the registers' value is interpreted as a hexadecimal number, each individual number represents one part of the register, and the number can be treated as a binary number (only 1 and 0 are relevant). This basically means that only eight settings are toggleable, and they are one nybble (four bits) apart.