User contributions for Starfrost

14:3014:30, 30 June 2025 diff hist +1,636 NV3 RAMIN No edit summary
13:2413:24, 30 June 2025 diff hist −1 NV3 No edit summary
13:1313:13, 30 June 2025 diff hist +861 N NV3 RAMIN Created page with "'''Instance memory''' (<code>RAMIN</code>, sometimes <code>PRAMIN</code>) is an area of VRAM where structures for objects to be operated on by the GPU are placed. It does not use traditional VRAM addressing, but instead uses its own addressing method which is fairly peculiar; at a high level, it is basically addressed in reverse, but in 16-byte increments; within those 16 bytes the addressing is done in a traditional order. RAMIN addresses can be converted to VRAM addres..."
10:2410:24, 30 June 2025 diff hist +418 NV3 memory mapping No edit summary

20:5320:53, 20 June 2025 diff hist +8 VBIOS No edit summary current
20:5320:53, 20 June 2025 diff hist 0 VBIOS No edit summary
19:4619:46, 20 June 2025 diff hist +54 VBIOS rewording
15:1315:13, 20 June 2025 diff hist +117 VBIOS No edit summary
15:1215:12, 20 June 2025 diff hist +26 VBIOS No edit summary
15:1215:12, 20 June 2025 diff hist +31 VBIOS No edit summary
15:1115:11, 20 June 2025 diff hist +1,394 VBIOS No edit summary
14:4414:44, 20 June 2025 diff hist +5,924 N VBIOS Created page with "The '''Video BIOS''' is a read-only memory of some kind (sometimes flash memory or EEPROM) on Nvidia cards (at least up to the Turing architecture and possibly later, although it was mostly only used for legacy compatibility reasons by then) that initialises the GPU, runs basic POST tests, and most critically, provides compatibility with the minimum expected range of graphics modes that all operating systems are known to support - typically this is the VBE 3.0 specificat..."

01:2501:25, 23 May 2025 diff hist +780 N NV3 memory mapping Created page with "Understanding the memory mapping of the NV3 is critical for understanding its overall operation. The memory mapping architecture is implemented internally by the NV3 on-die memory controller and exposed to the user via the configuration register interface of the Peripheral Connect Interface (PCI) bus and its siblings and successors, such as AGP (or in later models, PCIe). Two of the maximum six base address registers are exposed via the configuration registers, BAR0 and..."

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