User contributions for Starfrost

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A user with 407 edits. Account created on 15 April 2025.

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01:2501:25, 23 May 2025 diff hist +780 N NV3 memory mapping Created page with "Understanding the memory mapping of the NV3 is critical for understanding its overall operation. The memory mapping architecture is implemented internally by the NV3 on-die memory controller and exposed to the user via the configuration register interface of the Peripheral Connect Interface (PCI) bus and its siblings and successors, such as AGP (or in later models, PCIe). Two of the maximum six base address registers are exposed via the configuration registers, BAR0 and..."

20:4620:46, 20 May 2025 diff hist −2 NV3 No edit summary
20:4620:46, 20 May 2025 diff hist +2 NV3 No edit summary
20:4520:45, 20 May 2025 diff hist −1 NV3 No edit summary
20:4520:45, 20 May 2025 diff hist +6 NV3 No edit summary

13:0613:06, 18 May 2025 diff hist +2 Main Page No edit summary

11:5811:58, 17 May 2025 diff hist −6 NV3 PMC No edit summary
11:5811:58, 17 May 2025 diff hist −6 NV3 PMC No edit summary
11:5811:58, 17 May 2025 diff hist +26 NV3 PMC No edit summary
11:5611:56, 17 May 2025 diff hist +22 NV3 PMC No edit summary
11:5411:54, 17 May 2025 diff hist +42 NV3 PMC No edit summary
00:1300:13, 17 May 2025 diff hist +302 NV3 No edit summary
00:1000:10, 17 May 2025 diff hist +43 NV3 No edit summary
00:0900:09, 17 May 2025 diff hist +49 NV3 PMC No edit summary
00:0800:08, 17 May 2025 diff hist +20 NV3 PMC No edit summary
00:0700:07, 17 May 2025 diff hist −4 NV3 PMC No edit summary
00:0500:05, 17 May 2025 diff hist +250 NV3 PMC No edit summary
00:0300:03, 17 May 2025 diff hist 0 NV3 PMC No edit summary
00:0300:03, 17 May 2025 diff hist +16 NV3 PMC No edit summary
00:0200:02, 17 May 2025 diff hist −1 NV3 PMC No edit summary
00:0100:01, 17 May 2025 diff hist −3 NV3 PMC No edit summary
00:0100:01, 17 May 2025 diff hist +2,811 NV3 PMC No edit summary

23:3523:35, 16 May 2025 diff hist +16 NV3 PMC No edit summary
23:3423:34, 16 May 2025 diff hist +2 NV3 PMC No edit summary
23:3323:33, 16 May 2025 diff hist +298 NV3 PMC No edit summary
23:3023:30, 16 May 2025 diff hist +3,951 NV3 PMC No edit summary
23:1423:14, 16 May 2025 diff hist −27 NV3 PMC No edit summary
23:1423:14, 16 May 2025 diff hist +49 NV3 PMC various fixes
23:1223:12, 16 May 2025 diff hist +4,848 NV3 PMC di
22:0422:04, 16 May 2025 diff hist +53 NV3 No edit summary
20:4520:45, 16 May 2025 diff hist −183 Software Undo revision 177 by Starfrost (talk) Tag: Undo
20:4520:45, 16 May 2025 diff hist +183 Software No edit summary Tag: Reverted

23:4123:41, 14 May 2025 diff hist +45 NV3 (QTM) No edit summary current
23:4023:40, 14 May 2025 diff hist +6 NV3 (QTM) No edit summary
23:3923:39, 14 May 2025 diff hist 0 NV3 (QTM) No edit summary
23:3923:39, 14 May 2025 diff hist +106 NV3 (QTM) No edit summary

21:5221:52, 13 May 2025 diff hist +100 Software No edit summary
21:5221:52, 13 May 2025 diff hist +302 Software No edit summary

00:2800:28, 11 May 2025 diff hist +37 NV3 PMC No edit summary

14:0714:07, 8 May 2025 diff hist +33 Emulation status No edit summary

16:0616:06, 7 May 2025 diff hist +56 NV3 No edit summary
16:0516:05, 7 May 2025 diff hist +22 Main Page No edit summary
16:0416:04, 7 May 2025 diff hist +39 Main Page No edit summary
15:1415:14, 7 May 2025 diff hist +503 N Emulation status Created page with "This page details the emulation status for various NVIDIA GPUs. == NV3 == Emulation is '''partially working'''. Most of the pipeline exists, the GPU is detected and drivers initialise on all known supported operating systems, and 2D partially works. However, serious issues understanding the screen to screen blit behaiour are preventing this part from working. Additionally, the DMA engine, required for 3D, is not yet emulated correctly. == NV4 == Very early research and..."

19:5519:55, 6 May 2025 diff hist +56 Hardware errata No edit summary
19:5519:55, 6 May 2025 diff hist +380 NV3 PMC No edit summary
01:3901:39, 6 May 2025 diff hist +337 N NV3 PMC Created page with "'''PMC''' ('''M'''aster '''C'''ontrol) is the subsystem that controls all of the other subsystems within Nvidia-based GPUs. The NV3 version is fairly basic: it stores some manufacture-time configuration info, allows disabling and enabling interrupts, reading and writing interrupt status and enabling and disabling most other subsystems."

19:3019:30, 1 May 2025 diff hist +107 Hardware errata No edit summary

23:4323:43, 29 April 2025 diff hist +25 Template:GPUs No edit summary current
23:4323:43, 29 April 2025 diff hist +601 Template:GPUs No edit summary

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