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00:5300:53, 18 August 2025 GB1xx/GB2xx (hist | edit) [496 bytes] Starfrost (talk | contribs) (Created page with "{{Template:Infobox GPU |title='''GB1xx/GB2xx''' |architecture=Blackwell |branding=RTX 50-series, Nvidia Bxxx |announcement_date=18 March 2024 |release_date=Late 2024 (datacenter); 30 January 2025 (consumer) |end_of_production= |buses_supported=PCIe |directx_version=12 Ultimate |opengl_version=4.6 (+Vulkan 1.3) }} '''Blackwell''' is NVIDIA's current GPU architecture for artificial intelligence and gaming. It is "super duper advanced" according to noted self-appointed gen...")

18:5218:52, 7 August 2025 NV3 configuration (hist | edit) [4,690 bytes] Starfrost (talk | contribs) (Created page with "There are several different ways that an NV3-based GPU can be configured, depending on the level of flexibility required and who is configuring it. Configuration is done at either the OEM card design level, the manufacture time of the chip, or at the VBIOS or driver level. Each of these have their own mechanisms for configuration; some appear to be burned in with a focused ion beam (FIB)-type situation, others use physical solder-bridged jumpers or other similar mechanis...")

21:5821:58, 19 July 2025 NV1 known models (hist | edit) [1,530 bytes] Starfrost (talk | contribs) (Created page with "This is a list of known card models of the NVidia NV1. Attempts have been made to sort the companies by number of units sold. === Diamond Multimedia === {| class="wikitable" |+ Model information |- ! Brand name !! RAM type !! RAM amount !! Chip branding |- | Edge 3D 2120 || DRAM || 1 MB || STG2000X |- | Edge 3D 2200 || DRAM || 1 MB || STG2000X (usually) |- | Edge 3D 3240 || VRAM || 2 MB || NV1 |- | Edge 3D 3400 || VRAM || 4 MB (2MB on "3D Memory Module") || NV1 |} ===...")

00:2500:25, 4 July 2025 NV1 known units (hist | edit) [1,532 bytes] Starfrost (talk | contribs) (Created page with "Due to the Digital Rights Management engine on the NV1, the NV1 stores a unique chip token that allows the unique identification of an NV1 chip and is hashed with the RAMPW using the 64-bit DES-based crypto engine. These are the known list of Nvidia NV1 units. {| class="wikitable" |+ Caption text |- ! ChipToken !! Straps !! <code>NV_PMC_BOOT_0</code> !! <code>NV_PFB_BOOT_0</code> !! VRAM amount !! Branding (STG2000X/NV1) |- | <code>0xE5219C...")

13:1313:13, 30 June 2025 NV3 RAMIN (hist | edit) [2,498 bytes] Starfrost (talk | contribs) (Created page with "'''Instance memory''' (<code>RAMIN</code>, sometimes <code>PRAMIN</code>) is an area of VRAM where structures for objects to be operated on by the GPU are placed. It does not use traditional VRAM addressing, but instead uses its own addressing method which is fairly peculiar; at a high level, it is basically addressed in reverse, but in 16-byte increments; within those 16 bytes the addressing is done in a traditional order. RAMIN addresses can be converted to VRAM addres...")

14:4414:44, 20 June 2025 VBIOS (hist | edit) [7,554 bytes] Starfrost (talk | contribs) (Created page with "The '''Video BIOS''' is a read-only memory of some kind (sometimes flash memory or EEPROM) on Nvidia cards (at least up to the Turing architecture and possibly later, although it was mostly only used for legacy compatibility reasons by then) that initialises the GPU, runs basic POST tests, and most critically, provides compatibility with the minimum expected range of graphics modes that all operating systems are known to support - typically this is the VBE 3.0 specificat...")

01:2501:25, 23 May 2025 NV3 memory mapping (hist | edit) [17,722 bytes] Starfrost (talk | contribs) (Created page with "Understanding the memory mapping of the NV3 is critical for understanding its overall operation. The memory mapping architecture is implemented internally by the NV3 on-die memory controller and exposed to the user via the configuration register interface of the Peripheral Connect Interface (PCI) bus and its siblings and successors, such as AGP (or in later models, PCIe). Two of the maximum six base address registers are exposed via the configuration registers, BAR0 and...")

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