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21:5821:58, 19 July 2025 NV1 known models (hist | edit) [1,530 bytes] Starfrost (talk | contribs) (Created page with "This is a list of known card models of the NVidia NV1. Attempts have been made to sort the companies by number of units sold. === Diamond Multimedia === {| class="wikitable" |+ Model information |- ! Brand name !! RAM type !! RAM amount !! Chip branding |- | Edge 3D 2120 || DRAM || 1 MB || STG2000X |- | Edge 3D 2200 || DRAM || 1 MB || STG2000X (usually) |- | Edge 3D 3240 || VRAM || 2 MB || NV1 |- | Edge 3D 3400 || VRAM || 4 MB (2MB on "3D Memory Module") || NV1 |} ===...")

00:2500:25, 4 July 2025 NV1 known units (hist | edit) [1,533 bytes] Starfrost (talk | contribs) (Created page with "Due to the Digital Rights Management engine on the NV1, the NV1 stores a unique chip token that allows the unique identification of an NV1 chip and is hashed with the RAMPW using the 64-bit DES-based crypto engine. These are the known list of Nvidia NV1 units. {| class="wikitable" |+ Caption text |- ! ChipToken !! Straps !! <code>NV_PMC_BOOT_0</code> !! <code>NV_PFB_BOOT_0</code> !! VRAM amount !! Branding (STG2000X/NV1) |- | <code>0xE5219C...")

13:1313:13, 30 June 2025 NV3 RAMIN (hist | edit) [2,498 bytes] Starfrost (talk | contribs) (Created page with "'''Instance memory''' (<code>RAMIN</code>, sometimes <code>PRAMIN</code>) is an area of VRAM where structures for objects to be operated on by the GPU are placed. It does not use traditional VRAM addressing, but instead uses its own addressing method which is fairly peculiar; at a high level, it is basically addressed in reverse, but in 16-byte increments; within those 16 bytes the addressing is done in a traditional order. RAMIN addresses can be converted to VRAM addres...")

14:4414:44, 20 June 2025 VBIOS (hist | edit) [7,554 bytes] Starfrost (talk | contribs) (Created page with "The '''Video BIOS''' is a read-only memory of some kind (sometimes flash memory or EEPROM) on Nvidia cards (at least up to the Turing architecture and possibly later, although it was mostly only used for legacy compatibility reasons by then) that initialises the GPU, runs basic POST tests, and most critically, provides compatibility with the minimum expected range of graphics modes that all operating systems are known to support - typically this is the VBE 3.0 specificat...")

01:2501:25, 23 May 2025 NV3 memory mapping (hist | edit) [17,680 bytes] Starfrost (talk | contribs) (Created page with "Understanding the memory mapping of the NV3 is critical for understanding its overall operation. The memory mapping architecture is implemented internally by the NV3 on-die memory controller and exposed to the user via the configuration register interface of the Peripheral Connect Interface (PCI) bus and its siblings and successors, such as AGP (or in later models, PCIe). Two of the maximum six base address registers are exposed via the configuration registers, BAR0 and...")

15:1415:14, 7 May 2025 Emulation status (hist | edit) [609 bytes] Starfrost (talk | contribs) (Created page with "This page details the emulation status for various NVIDIA GPUs. == NV3 == Emulation is '''partially working'''. Most of the pipeline exists, the GPU is detected and drivers initialise on all known supported operating systems, and 2D partially works. However, serious issues understanding the screen to screen blit behaiour are preventing this part from working. Additionally, the DMA engine, required for 3D, is not yet emulated correctly. == NV4 == Very early research and...")

01:3901:39, 6 May 2025 NV3 PMC (hist | edit) [13,107 bytes] Starfrost (talk | contribs) (Created page with "'''PMC''' ('''M'''aster '''C'''ontrol) is the subsystem that controls all of the other subsystems within Nvidia-based GPUs. The NV3 version is fairly basic: it stores some manufacture-time configuration info, allows disabling and enabling interrupts, reading and writing interrupt status and enabling and disabling most other subsystems.")

00:0300:03, 28 April 2025 PTIMER (hist | edit) [4,861 bytes] Starfrost (talk | contribs) (Created page with "'''PTIMER''' is a hardware subsystem that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the NV1. It is required to, among other things, f...")

22:3822:38, 27 April 2025 Hardware errata (hist | edit) [4,416 bytes] Starfrost (talk | contribs) (Created page with "This is a list of known hardware errata in Nvidia graphics cards == Shared across multiple GPUs == == NV3 == === Early VBIOS bugs === While not technically a hardware errata, most likely due to an unknown issue with the video BIOS code in certain very early NVidia RIVA 128 units, certain VGA functions are broken. This causes garbage characters to appear inside of the Windows 98 Startup menu while trying to boot from CD-ROM. This bug is known to exist in very early S...")

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