NV3 RAMIN: Difference between revisions
No edit summary |
No edit summary |
||
| Line 1: | Line 1: | ||
'''Instance memory''' (<code>RAMIN</code>, sometimes <code>PRAMIN</code>) is an area of VRAM where structures for objects to be operated on by the GPU are placed; it is technically considered to be a section of [[NV3 PFIFO|<code>PFIFO</code> | '''Instance memory''' (<code>RAMIN</code>, sometimes <code>PRAMIN</code>) is an area of VRAM where structures for objects to be operated on by the GPU are placed; it is technically considered to be a section of [[NV3 PFIFO|<code>PFIFO</code>]], since it deals with object submission, but it is useful to understand it as a separate syste. It does not use traditional VRAM addressing, but instead uses its own addressing method which is fairly peculiar; at a high level, it is basically identical to VRAM, but addressed in reverse in 16-byte increments; within those 16 bytes the addressing is done in a traditional order, but the actual 16 byte "windows" are addressed in reverse. RAMIN addresses can be converted to VRAM addresses using the following formula: | ||
<pre> | <pre> | ||
Latest revision as of 00:25, 4 July 2025
Instance memory (RAMIN, sometimes PRAMIN) is an area of VRAM where structures for objects to be operated on by the GPU are placed; it is technically considered to be a section of PFIFO, since it deals with object submission, but it is useful to understand it as a separate syste. It does not use traditional VRAM addressing, but instead uses its own addressing method which is fairly peculiar; at a high level, it is basically identical to VRAM, but addressed in reverse in 16-byte increments; within those 16 bytes the addressing is done in a traditional order, but the actual 16 byte "windows" are addressed in reverse. RAMIN addresses can be converted to VRAM addresses using the following formula:
addr &= (vram_max - 1);
addr ^= (vram_max - 0x10);
addr >>= 2; // what
Or expressed in a more linguistic way:
real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size)
where reversal_unit_size is equal to 16.
When working with real NV3 hardware, you do not need to do this operation, as PCI BAR1 contains a mirror of RAMIN starting at 0xC00000, with the hardware doing the address translation for you. This is used by the drivers in order to communicate directly with RAMIN and control the GPU's internal state without having to use object submission system (writing object methods will manipulate RAMIN directly too).
RAMIN Structures
The RAMIN area contains various structures that are used by the GPU to maintain its internal state as well as to store and operate on user-submitted objects. While a summary of the functionality of each area of RAMIN is provided here, please consult the pages for each relevant area for more detailed information as well as how to program these areas.
RAMHT
Main article: NV3 RAMHT
RAMFC
Main article: NV3 RAMFC
RAMRO
Main article: NV3 RAMRO
RAMAU (Revision A only)
Main article: NV3 RAMAU
RAMIN Configuration
The sizes and locations of the various structures within the RAMIN can be configured by various registers in PFIFO.
RAMIN Power-On State
When the GPU is powered up, as well as when the PMC PMC_ENABLE register is set to zero, the RAMIN configuration registers will be forced to certain known-safe values.