NV3

NV3

Branding	RIVA 128
Architecture	NV3
Release date	25 August 1997
End of production	late(?) 1998
PCI vendor ID	12d2 (SGS/Nvidia)
PCI device ID	0018
Announcement date	25 April 1997
DirectX hardware supported version	5.0
OpenGL hardware supported version	1.1

The NV3 architecture is Nvidia's third-generation graphics architecture, designed from 1996 to 1997 and released at the end of August 1997 under the Riva 128 branding. It was designed by a team under the direction of David Kirk and was designed to be the "fastest triangle renderer on earth" at the time while being able to be designed in a very short time (due to Nvidia's near-bankruptcy during the period of its design), provide 2D acceleration with full, non-emulated (unlike the NV1) VGA compatibility, and at a reasonably low price. It did achieve this goal, although with many caveats: the graphics image quality was not as good as some rival cards (e.g. the 3dfx Voodoo), there are a few minor missing features that were considered important at the time like trilinear texture filtering. Most importantly, it was by far the fastest 2D/3D combo card, and by some measures the fastest 3D card full stop, available at the time, since Voodoos before the Voodoo Banshee, excluding the disastrous Voodoo Rush, can only accelerate 3D applications (barring specialised "3D-on-2D" drivers), and even then only in fullscreen mode. Even when it was not used as a 3D card, it was often used as a passthrough for a 3dfx Voodoo card (despite the Riva 128 having almost equal 3D capabilities). While the Riva 128 had worse CPU scaling, performing slower on slower CPUs, despite its more complete triangle setup engine, its overall speed was slightly faster (especially on smaller triangles), albeit with somewhat worse image quality (in 1997, having a usable image at all was considered decent due to catastrophe cards like the Alliance Semiconductor aT3D, but by 1999 it was considered almost bad image quality); it could also load much larger textures (2048x2048, although impractical due to the limited VRAM, as opposed to the Voodoo's 256x256). Most NV3-architecture based graphics cards ran at a default clock speed of 100 Mhz (although some TSMC-manufactured NV3T chips are specified to run at 90 Mhz, and overclocking up to around 120 Mhz was often done safely with the requisite improvements in performance), with the pixel clock ranging up to a maximum of 230 (NV3) or 260 (NV3T) Mhz. A maximum of 4 megabytes of Video RAM is supported and the card can be run off of either the PCI 2.1 (at 66 Megahertz bus speed) or AGP 1X buses.

The 2D acceleration of the NV3 architecture provides full VGA, VBE 3.0, and accelerated 2D support, Windows GDI acceleration (including full GDI ternary bitblit ROP support), point, line and rectangle drawing, image rendering, screen to screen blit with up to four manipulatable buffers (although only two are used for this purpose in practice in the Nvidia drivers), image scaling and stretching, rendering at an 8 to 32 bits per pixel colour depth at a maximum theoretical resolution of 2048*1536 and maximum practical resolution of either 1600*1200 (NV3) or 1920*1200 (NV3T), although this requires reducing the colour depth to 16bpp or lower. Other supported features of the 2D graphics pipeline include colour conversion (including RGB10, YUV420 and 422, and palette-based colour formats), colour-expansion and downconversion, color-expanded bitblit for optimised text bitmap rendering, color key, plane mask and TV-out functionality with video overlay support (via the on-board "Mediaport"). Buffers can be anywhere in VRAM with any pitch and any supported colour format. The card's VGA support is provided via a modified Weitek VGA core that Nvidia licensed.

There also exists within the NV3 architecture a fairly robust (for the time), mostly Direct3D 5.0-compliant and OpenGL 1.1 3D rendering implementation. Flat shading, gouraud shading, perspective-corrected (via submission of a homogenous 1/W value to the GPU to be used for perspective correction: the GPU will not perform this itself) bilinear-filtered texture mapping, per polygon and later per-pixel (with a driver update) mip-mapping, texture interpolation and wrapping (supported texture wrapping modes are clamping, mirroring and wrapping, and they can be set separately for both the U and V coordinate), most Direct3D 5.0 rendering ROPs (additive blending from the Direct3D 5.0 specification is missing and a few others), meshes, specular highlight, a 16-bit Z-buffer and 8-bit stencil buffer (interleaved in what was called a "zeta buffer" for optimisation reasons), alpha-buffering for alpha blending, hardware fog (vertex fog - applying the fog colour and intensity at a vertex level - is implemented in hardware, whereas table fog - the slightly higher quality version where the fog colour is applied at output pixel levle - is emulated using vertex fog) with 24-bit fog colour; while triangle setup (span interpolation and similar operations) are accelerated, transformation and lighting^[1] are not (this would have to wait for NV10). Most of the interface to the NV3's 3D engine is implemented via the NV_D3D0Z class; the interface to this class is via various methods for the control of all of the above features and then the submission of X, Y, Z, M (the aforementioned homogenous 1/W coordinte), U and V (for textures) coordinates for up to 128 triangles at a time. Although the output pixel format appears to be always 32-bit, only the 16-bit (not even 8-bit; the drivers convert any non 16-bit texture to 16-bit) A4R4G4B4, A1R5G5B5, R5G5B5 and, via registry tweaks in the Direct3D driver, R5G6B5 texture formats can be loaded; the largest texture size that can be loaded is 2048x2048, although in practice this is most likely done by splitting up the large texture into smaller textures, since a 2048x2048 texture (even at just 8bpp) is a minimum of 4 MB - too small to fit in the regular NV3 VRAM, and in a supported texture format will be 8 MB; too large for any variant of the NV3 architecture to support. Multitexturing is not supported; only a single texture can be supplied via the NV_D3D0Z class methods at a time. Up to 128 triangles can be submitted at a time, therefore it is a good idea to ensure the area covered by only one texture is close to a multiple of 128 while optimising for this graphics card.

The PIO mode from the NV1 for object submission remains and is used for most basic 2D drivers, however a new DMA mode is added for faster object submission and higher three-dimensional graphics throughput.

NV3T

NV3T

Branding	RIVA 128 ZX
Architecture	NV3T
Release date	Q2 1998
End of production	mid-1999
PCI vendor ID	12d2 (SGS/Nvidia)
PCI device ID	0018 (0019 if ACPI is enabled)
Announcement date	27 February 1998
DirectX hardware supported version	5.0
OpenGL hardware supported version	1.1

The NV3T (NV3 Turbo; also known as NV3 revision C), commercialised as the RIVA 128 ZX (briefly called "RIVA 128 Turbo"), is a respin of the NV3 to allow for higher RAMDAC clock speeds (260Mhz) and more Video RAM to compete with the Intel i740. It expands the maximum amount of video RAM to 8MB, makes PFIFO's CACHE1 64 units deep instead of 32, allows for resolutions above 1600x1200 by both the aforementioned higher clocked RAMDAC in both the VGA BIOS and the drivers, and can run 3D at higher resolutions due to its higher amount of video RAM. Additionally, this was the first Nvidia GPU (other than the very few NV2's manfuactured) to be manufactured by a manufacturer that is not STMicroelectronics (then SGS-Thomson): the RIVA 128 ZX was manufactured by TSMC; it appears that they may not have had equal yields to ST (despite ST's yield crisis at the time), as some NV3Ts manufactured by TSMC are downclocked to 90 megahertz.

Tutorials

NV3 Getting Started - How to program the RIVA 128, the real way

Hardware subsystems

NV3 and NV3T share the same hardware subsystems:

• PMC - The part that controls everything else

• PGRAPH - 2D/3D graphics rendering engine (name comes from "Scene graph")
  • Graphics objects - Available graphics objects
• NV3 rendering pipeline - How rendering happens
  • NV3 object submission - How rendering starts
  • NV_USER - How to submit objects using Programmed I/O#
  • PFIFO - FIFO for optimised graphics engine submission
  • DMA Engine - How to submit objects using DMA
  • PFB - Framebuffer interface
  • RAMIN - Where graphics objects get stored
  • RAMHT - How you find graphics objects
  • RAMFC - Where the objects go for DMA context switching
  • RAMRO - Where objects go when it all goes wrong
  • RAMAU - Remnants of what was meant to be
  • Notification Engine - How to tell software the state of the hardware
  • PRAMDAC - RAMDAC for clocks, memory timings, CLUT, and sending the framebuffer to the TV or monitor
• PVIDEO - Video overlay and control
• PME - Mediaport - Lets you plug in an external MPEG decoder
• PRMCIO - CRTC for controlling a connected CRT display
• PRMVIO - Legacy VGA support, courtesy of Weitek
• PTIMER - Programmable interval timer
• PDFB - Just a dumb framebuffer
• Real-mode access - Access the GPU from real mode
• VBIOS - Initialisation, POST, VGA and VESA
• PROM - Read from the Video BIOS
• PDAC - Optional external DAC support
• Configuration#Manufacture-time configuration - Read the manufacturer, stepping, bus size, bus and more of your GPU
• Configuration#Straps - OEM-level configuration

Notes

^ The NV_PGRAPH_DEBUG_2 register's bit 15 is officially called LIGHTING_3D_ENABLED, and the NV_PGRAPH_STATUS register's 26th bit is called NV_PGRAPH_STATUS_LIGHTING which can be "busy" or not. It doesn't appear that these have any real effect on how the graphics hardware behaves: they may be leftovers from NV2.