NV1 object classes

This is the list of object classes that can be submitted via PFIFO on NV1.

Note: This is the internal class interface. The Resource Manager provides a different class interface before NV4. These are the class IDs required to actually submit objects to the GPU hardware - the IDs must be shifted right by 12 bits to be submitted (in effect, they show up as 0x40-0x5F while viewing RAMHT in a hex editor, like on NV3)

Objects must first be submitted (see NV1 Object Submission and NV1 PFIFO). As many methods can be submitted as possible (methods are defined as offsets within the PIO subchannel allocated to the object), but methods need to be submitted in the right order for rendering to occur. There is no mapping between the number of objects rendered and the number of objects submiteted

It appears that PIO subchannels get mapped to write-only registers at (0x400000 + (0x10000 * class_id)) in MMIO - e.g. UBETA is at 0x410000.