NV3 memory mapping

Understanding the memory mapping of the NV3 is critical for understanding its overall operation.

The memory mapping architecture is implemented internally by the NV3 on-die memory controller and exposed to the user via the configuration register interface of the Peripheral Connect Interface (PCI) bus and its siblings and successors, such as AGP (or in later models, PCIe). Two of the maximum six base address registers are exposed via the configuration registers, BAR0 and BAR1. BAR0 contains a gigantic slab (16MB) of MMIO containing all registers, and BAR1, also 16MB, contains both a copy of the current framebuffer (or all of VRAM?) for dumb framebuffer use, and, at 0xC00000, instance memory mapped as it is intended to be addressed.