NV1 RMC: Difference between revisions
Created page with "Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In NV3 this system was replaced by the much simpler [[NV3 RMA|Real-mode Access] subsystem...." |
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Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] this system was replaced by the much simpler [[NV3 RMA|Real-mode Access] subsystem. | Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] this system was replaced by the much simpler [[NV3 RMA|Real-mode Access] subsystem. | ||
The VBIOS is exposed to MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760kb. HFor unknown reasons, the registers for this functionality have been to put the registers for this | The VBIOS is exposed to MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760kb. HFor unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be accssing the window settings at BAR0 <code>0x1400</code> | ||
== How to Use == | == How to Use == | ||
1. Write 4 | 1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code> | ||
2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. There is a separate windowing system for SVGA VRAM for some reason which allows you to map 0->1mb in 8kb blocks and has an additional feature where bit 12 toggles linear mappings or VGA bitplane mapping. This is odd, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation. | 2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. There is a separate windowing system for SVGA VRAM for some reason which allows you to map 0->1mb in 8kb blocks and has an additional feature where bit 12 toggles linear mappings or VGA bitplane mapping. This is odd, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation. | ||
3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use | 3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use | ||
4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again. | |||
The RMC mechanism internally works using DMA. The DMA settings can be changed via manipulating the value of the <code>NV_PBUS_RMC_DMA_0</code> register. A example of this would be changing the direction by flipping bit 26 and changing the tarhget DMA address by overwriting bits 23 through 0. | |||
== | == Register Reference == | ||
Revision as of 14:09, 25 December 2025
Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In NV3 this system was replaced by the much simpler [[NV3 RMA|Real-mode Access] subsystem.
The VBIOS is exposed to MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760kb. HFor unknown reasons, the registers for this functionality have been to put the registers for this in VGA VRAM (e.g. the window settings are at B1400, with the 8KB window starting at B2000), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be accssing the window settings at BAR0 0x1400
How to Use
1. Write the 4 characters GoNV to 0xB1E10
2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. There is a separate windowing system for SVGA VRAM for some reason which allows you to map 0->1mb in 8kb blocks and has an additional feature where bit 12 toggles linear mappings or VGA bitplane mapping. This is odd, because in later Nvidia GPUs (those that use the Weitek] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at A0000, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.
3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use
4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again.
The RMC mechanism internally works using DMA. The DMA settings can be changed via manipulating the value of the NV_PBUS_RMC_DMA_0 register. A example of this would be changing the direction by flipping bit 26 and changing the tarhget DMA address by overwriting bits 23 through 0.