GPU Clocking: Difference between revisions
Created page with "Any electronic device needs a clock source to operate, and Nvidia GPUs are no exception. In early nVIDIA GPU's, the system of generating phase-locked loops (PLL) was a derivative that used by the SGS-Thomson STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from NV1 until NV20. A partial break from this system was introduced with the implementation of mult..." |
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Any electronic device needs a clock source to operate, and | Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. | ||
=== Initial clock system (1995-2002) === | |||
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at MMIO address ranges between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers staring at <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be hardcoded by simply taking the signal coming directly from the on-board clock crystal, or configured via straps - in order to create the final clock speed using the following formula: | |||
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre> | |||
=== PLLs on the NV1 === | |||
The NV1 has three PLLs. | |||
==== Configuration ==== | |||
==Notes== | ==Notes== | ||
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies. | {{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br> | ||
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used. | |||
{{note|c|}} Only 19 bits are actually used | |||
Revision as of 17:02, 25 March 2026
Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from NV1 until NV20. A partial break from this system was introduced with the implementation of multi-stage clocks in NV30 and a full break was achieved with NV40's implementation of clock domains[1] .
Initial clock system (1995-2002)
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the PRAMDAC functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at MMIO address ranges between 0x680300 and 0x680FFF. In most cases (and in all cases prior to NV10), the registers staring at 0x680500 and ending at 0x6805FF are used for PLL configuration; each PLL has a 32-bit[2]
register assigned to it, and there is a second 32-bit register (typically at 0x68050C) that is used to configure these PLLs. Each PLL register is split into three dividers[3]
, with the low 8 bits making up MDIV, bits 15 through 8 making up NDIV, and a three-bit (bits 18 through 16) PDIV. These are combined with a base clock speed - which can be hardcoded by simply taking the signal coming directly from the on-board clock crystal, or configured via straps - in order to create the final clock speed using the following formula:
(base_clock_speed * NDIV) / (MDIV << PDIV)
PLLs on the NV1
The NV1 has three PLLs.
Configuration
Notes
^ Used to allow different parts of the GPU core to run at different clock frequencies.
^ The NV1 technically has a fourth divider, ODIV, but it is always set to a value of 1 and is effectively never used.
^ Only 19 bits are actually used