GPU Clocking

Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from NV1 until NV20. A partial break from this system was introduced with the implementation of multi-stage clocks in NV30 and a full break was achieved with NV40's implementation of clock domains^[1] .

Initial clock system (1995-2002)

The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the PRAMDAC functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between 0x680300 and 0x680FFF. In most cases (and in all cases prior to NV10), the registers starting at MMIO address 0x680500 and ending at 0x6805FF are used for PLL configuration; each PLL has a 32-bit^[2] register assigned to it, and there is a second 32-bit register (typically at 0x68050C) that is used to configure these PLLs. Each PLL register is split into three dividers^[3] , with the low 8 bits of the register making up MDIV, bits 15 through 8 making up NDIV, and a three-bit (bits 18 through 16) PDIV. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:

(base_clock_speed * NDIV) / (MDIV << PDIV)

For example, if the base clock speed is 10MHz, NDIV is 90, MDIV is 10 and PDIV is 1, the formula resolves as:

(10000000 * 90) / (10 << 1)

which resolves to exactly 45,000,000 Hz (or 45 MHz).

Additionally, via the configuration register at 0x60850C, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section.

PLLs on the NV1

The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divider; the first register is used to hold the MDIV, the second the NDIV, the third the ODIV and the last the PDIV

Clock sources on the NV1

PLL	Purpose	MMIO address	Notes
MPLL	The name means Memory PLL, but actually clocks both the GPU core and the Video RAM	DAC space 0x18-0x1C	Set by VBIOS scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: Video BIOS: NDIV=91, MDIV=11, PDIV=1 (50.033454 MHz), Drivers (if PLL command cannot be found in Video BIOS): NDIV=100, MDIV=14, PDIV=1 (43.2 MHz),
APLL	Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip	DAC space 0x14-0x17	Unknown
VPLL	Used to drive the video signal	DAC space 0x10-0x13	Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.

Configuration

On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of SGS_DAC_POWER_MGMT_B (SGS DAC register 0x000D), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL.

The other set of configuration which is available is contained within the lower four bits of SGS_DAC_CONFIG_1 (SGS DAC register 0x0005). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU can run at.

SGS_DAC_CONFIG_1 V PLL-related bits

Bit(s)	Name	Effect
4	Direction: off - output, on - input.	Not sure what this means. I don't know what reversing the "direction" of the VPLL would do.
3	Impedance: off - "low", on - "high"	No exact ohmage is provided. Possibly intended for board
2:0	Video clock display	0x00 - Divide by 1 (don't do anything) 0x01 - Divide by 2 0x02 - Divide by 4 0x03 - Divide by 8 0x04 - Divide by 16	Applies a post-divider to the VCLK after it is calculated. Resource Manager version 2.3 only uses dividers of one and two.

Notes

^ Used to allow different parts of the GPU core to run at different clock frequencies.
^ The NV1 technically has a fourth divider, ODIV, but it is always set to a value of 1 and is effectively never used. ^ Only 19 bits are actually used by these registers (except in NV1)