View source for NV1 RMC

Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons, the video BIOS has to run in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sitting on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA|Real-Mode Access]] subsystem. 

The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals, up to 32760KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>0xB1400</code>, with the 8KB window starting at <code>0xB2000</code>), therefore they have to allow this system to be transparently turned on and off. The regular GPU can access the RMC registers using the following formula: <code>0x1400 + (addr & 0xFF)</code>; an example of this would be accessing the window settings at BAR0 <code>0x1400</code>.

== How to Use ==
1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>.

2. Configure the windowing information (i.e. what 8KB range of MMIO you want your three sliding windows to point to) by writing <code>start position of window >> 13 bits</code> to <code>B1E40</code>. For unknown reasons, there is a separate windowing system for SVGA VRAM, which allows the user to map anywhere in the real-mode address space (1 MB) in 8KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]] core), the SVGA legacy VRAM is simply directly mapped into BAR0 at <code>0xA0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off-the-shelf STMicroelectronics VGA core combined with software emulation.

3. Do I/O by writing to the region from <code>0xB2000</code> to <code>0xB4000</code>, which will map to the first 8KB VGA window. Add <code>0x2000</code> for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32MB of M.IO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24KB (8KB per window and a maximum of three windows) can be accessed at any given time.

4. When you are done, write <code>NoNV</code> to <code>0xB1E10</code>, so that VGA VRAM is accessible again.

The RMC mechanism internally works using DMA. The DMA settings can be changed via manipulating the value of the <code>NV_PBUS_RMC_DMA_0</code> register. A example of this would be changing the direction by flipping bit 26 and changing the target DMA address by overwriting bits 23 through 0. 

== Register Reference ==