PTIMER - Revision history

Starfrost at 00:05, 28 April 2025

2025-04-28T00:05:55Z

← Older revision		Revision as of 00:05, 28 April 2025
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	'''PTIMER''' is a [[hardware subsystem]] that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the [[NV1]]. It is required to, among other things, for the graphics hardware to perform activities that involve waiting a defined amount of time, for the drivers to know when to poll for GPU state changes and many more things. All registers of PTIMER are located within the [[Memory mapping#PCI BAR0 - Core GPU MMIO\|main GPU MMIO]] area. In order to use the PTIMER correctly, the <code>PTIMER_NUMERATOR</code> and <code>PTIMER_DENOMINATOR</code> registers must be programmed to appropriate values. Then, the <code>PTIMER_ALARM</code> register must be set in order to set when the alarm is reset. Then, each clock cycle, the <code>PTIMER_TIME_0</code> (bits 31 through 5) and <code>PTIMER_TIME_1</code> (bits 28 through 0) will update based on the number of nanoseconds that have passed. This will occur at a rate set by the result of the calculation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code> (where MCLK is the [[NV3 PRAMDAC\|GPU core clock]] on NV3, and [[NV4 PRAMDAC\|memory clock]] on NV4 and later). When <code>PTIMER_TIME_1</code>{{ref\|a}} is equal to <code>PTIMER_ALARM</code>, the <code>PTIMER_INTR_ALARM</code> interrupt will be fired and <code>PTIMER_TIME_1</code> will be reset to zero (most likely, <code>PTIMER_TIME_0</code> is incremented at this time). Disabling this interrupt is possible, but extremely unwise: if you are running under nVIDIA's Resource Manager, the drivers will most likely immediately cease to work, since [[NV3 PFIFO\|PFIFO]] cache errors will never be caught, some I2C communication and several other critical events will not happen. Interrupts for the PTIMER subsystem cannot be turned off by using [[NV3 PMC\|PMC]]'s <code>PMC_INTERRUPT_ENABLE</code> register, nor can PTIMER be turned off using <code>PMC_ENABLE</code>.		'''PTIMER''' is a [[hardware subsystem]] that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the [[NV1]]. It is required to, among other things, for the graphics hardware to perform activities that involve waiting a defined amount of time, for the drivers to know when to poll for GPU state changes and many more things. All registers of PTIMER are located within the [[Memory mapping#PCI BAR0 - Core GPU MMIO\|main GPU MMIO]] area. In order to use the PTIMER correctly, the <code>PTIMER_NUMERATOR</code> and <code>PTIMER_DENOMINATOR</code> registers must be programmed to appropriate values. Then, the <code>PTIMER_ALARM</code> register must be set in order to set when the alarm is reset. Then, each clock cycle, the <code>PTIMER_TIME_0</code> (bits 31 through 5) and <code>PTIMER_TIME_1</code> (bits 28 through 0) will update based on the number of nanoseconds that have passed. This will occur at a rate set by the result of the calculation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code> (where MCLK is the [[NV3 PRAMDAC\|GPU core clock]] on NV3, and [[NV4 PRAMDAC\|memory clock]] on NV4 and later). When <code>PTIMER_TIME_1</code>{{ref\|a}} is equal to <code>PTIMER_ALARM</code>, the <code>PTIMER_INTR_ALARM</code> interrupt will be fired and <code>PTIMER_TIME_1</code> will be reset to zero (most likely, <code>PTIMER_TIME_0</code> is incremented at this time). Disabling this interrupt is possible, but extremely unwise: if you are running under nVIDIA's Resource Manager, the drivers will most likely immediately cease to work, since [[NV3 PFIFO\|PFIFO]] cache errors will never be caught, some I2C communication and several other critical events will not happen. Interrupts for the PTIMER subsystem cannot be turned off by using [[NV3 PMC\|PMC]]'s <code>PMC_INTERRUPT_ENABLE</code> register, nor can PTIMER be turned off using the global subsystem status in <code>PMC_ENABLE</code>.

	== Registers ==		== Registers ==

Starfrost at 00:04, 28 April 2025

2025-04-28T00:04:50Z

← Older revision		Revision as of 00:04, 28 April 2025
Line 1:		Line 1:
	'''PTIMER''' is a [[hardware subsystem]] that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the [[NV1]]. It is required to, among other things, for the graphics hardware to perform activities that involve waiting a defined amount of time, for the drivers to know when to poll for GPU state changes and many more things. All registers of PTIMER are located within the [[Memory mapping#PCI BAR0 - Core GPU MMIO\|main GPU MMIO]] area. In order to use the PTIMER correctly, the <code>PTIMER_NUMERATOR</code> and <code>PTIMER_DENOMINATOR</code> registers must be programmed to appropriate values. Then, the <code>PTIMER_ALARM</code> register must be set in order to set when the alarm is reset. Then, each clock cycle, the <code>PTIMER_TIME_0</code> (bits 31 through 5) and <code>PTIMER_TIME_1</code> (bits 28 through 0) will update based on the number of nanoseconds that have passed. This will occur at a rate set by the result of the calculation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code> (where MCLK is the [[NV3 PRAMDAC\|GPU core clock]] on NV3, and [[NV4 PRAMDAC\|~~Memory~~ clock]] on NV4 and later). When <code>PTIMER_TIME_1</code>{{ref\|a}} is equal to <code>PTIMER_ALARM</code>, the <code>PTIMER_INTR_ALARM</code> interrupt will be fired and <code>PTIMER_TIME_1</code> will be reset to zero (most likely, <code>PTIMER_TIME_0</code> is incremented at this time). Disabling this interrupt is possible, but extremely unwise: if you are running under nVIDIA's Resource Manager, the drivers will most likely immediately cease to work, since [[NV3 PFIFO\|PFIFO]] cache errors will never be caught, some I2C communication and several other critical events will not happen. Interrupts for the PTIMER subsystem cannot be turned off by using [[NV3 PMC\|PMC]]'s <code>PMC_INTERRUPT_ENABLE</code> register, nor can PTIMER be turned off using <code>PMC_ENABLE</code>.		'''PTIMER''' is a [[hardware subsystem]] that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the [[NV1]]. It is required to, among other things, for the graphics hardware to perform activities that involve waiting a defined amount of time, for the drivers to know when to poll for GPU state changes and many more things. All registers of PTIMER are located within the [[Memory mapping#PCI BAR0 - Core GPU MMIO\|main GPU MMIO]] area. In order to use the PTIMER correctly, the <code>PTIMER_NUMERATOR</code> and <code>PTIMER_DENOMINATOR</code> registers must be programmed to appropriate values. Then, the <code>PTIMER_ALARM</code> register must be set in order to set when the alarm is reset. Then, each clock cycle, the <code>PTIMER_TIME_0</code> (bits 31 through 5) and <code>PTIMER_TIME_1</code> (bits 28 through 0) will update based on the number of nanoseconds that have passed. This will occur at a rate set by the result of the calculation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code> (where MCLK is the [[NV3 PRAMDAC\|GPU core clock]] on NV3, and [[NV4 PRAMDAC\|memory clock]] on NV4 and later). When <code>PTIMER_TIME_1</code>{{ref\|a}} is equal to <code>PTIMER_ALARM</code>, the <code>PTIMER_INTR_ALARM</code> interrupt will be fired and <code>PTIMER_TIME_1</code> will be reset to zero (most likely, <code>PTIMER_TIME_0</code> is incremented at this time). Disabling this interrupt is possible, but extremely unwise: if you are running under nVIDIA's Resource Manager, the drivers will most likely immediately cease to work, since [[NV3 PFIFO\|PFIFO]] cache errors will never be caught, some I2C communication and several other critical events will not happen. Interrupts for the PTIMER subsystem cannot be turned off by using [[NV3 PMC\|PMC]]'s <code>PMC_INTERRUPT_ENABLE</code> register, nor can PTIMER be turned off using <code>PMC_ENABLE</code>.

	== Registers ==		== Registers ==

Starfrost at 00:04, 28 April 2025

2025-04-28T00:04:38Z

← Older revision		Revision as of 00:04, 28 April 2025
Line 1:		Line 1:
	'''PTIMER''' is a [[hardware subsystem]] that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the [[NV1]]. It is required to, among other things, for the graphics hardware to perform activities that involve waiting a defined amount of time, for the drivers to know when to poll for GPU state changes and many more things. In order to use the PTIMER ~~CORRECTLY~~, the <code>PTIMER_NUMERATOR</code> and <code>PTIMER_DENOMINATOR</code> registers must be programmed to appropriate values. Then, the <code>PTIMER_ALARM</code> register must be set in order to set when the alarm is reset. Then, each clock cycle, the <code>PTIMER_TIME_0</code> (bits 31 through 5) and <code>PTIMER_TIME_1</code> (bits 28 through 0) will update based on the number of nanoseconds that have passed. This will occur at a rate set by the result of the calculation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code> (where MCLK is the [[NV3 PRAMDAC\|GPU core clock]] on NV3, and [[NV4 PRAMDAC\|Memory clock]] on NV4 and later). When <code>PTIMER_TIME_1</code>{{ref\|a}} is equal to <code>PTIMER_ALARM</code>, the <code>PTIMER_INTR_ALARM</code> interrupt will be fired and <code>PTIMER_TIME_1</code> will be reset to zero (most likely, <code>PTIMER_TIME_0</code> is incremented at this time). Disabling this interrupt is possible, but extremely unwise: if you are running under nVIDIA's Resource Manager, the drivers will most likely immediately cease to work, since [[NV3 PFIFO\|PFIFO]] cache errors will never be caught, some I2C communication and several other critical events will not happen. Interrupts for the PTIMER subsystem cannot be turned off by using [[NV3 PMC\|PMC]]'s <code>PMC_INTERRUPT_ENABLE</code> register, nor can PTIMER be turned off using <code>PMC_ENABLE</code>.		'''PTIMER''' is a [[hardware subsystem]] that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the [[NV1]]. It is required to, among other things, for the graphics hardware to perform activities that involve waiting a defined amount of time, for the drivers to know when to poll for GPU state changes and many more things. All registers of PTIMER are located within the [[Memory mapping#PCI BAR0 - Core GPU MMIO\|main GPU MMIO]] area. In order to use the PTIMER correctly, the <code>PTIMER_NUMERATOR</code> and <code>PTIMER_DENOMINATOR</code> registers must be programmed to appropriate values. Then, the <code>PTIMER_ALARM</code> register must be set in order to set when the alarm is reset. Then, each clock cycle, the <code>PTIMER_TIME_0</code> (bits 31 through 5) and <code>PTIMER_TIME_1</code> (bits 28 through 0) will update based on the number of nanoseconds that have passed. This will occur at a rate set by the result of the calculation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code> (where MCLK is the [[NV3 PRAMDAC\|GPU core clock]] on NV3, and [[NV4 PRAMDAC\|Memory clock]] on NV4 and later). When <code>PTIMER_TIME_1</code>{{ref\|a}} is equal to <code>PTIMER_ALARM</code>, the <code>PTIMER_INTR_ALARM</code> interrupt will be fired and <code>PTIMER_TIME_1</code> will be reset to zero (most likely, <code>PTIMER_TIME_0</code> is incremented at this time). Disabling this interrupt is possible, but extremely unwise: if you are running under nVIDIA's Resource Manager, the drivers will most likely immediately cease to work, since [[NV3 PFIFO\|PFIFO]] cache errors will never be caught, some I2C communication and several other critical events will not happen. Interrupts for the PTIMER subsystem cannot be turned off by using [[NV3 PMC\|PMC]]'s <code>PMC_INTERRUPT_ENABLE</code> register, nor can PTIMER be turned off using <code>PMC_ENABLE</code>.

	== Registers ==		== Registers ==

Starfrost: Created page with "'''PTIMER''' is a hardware subsystem that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the NV1. It is required to, among other things, f..."

2025-04-28T00:03:11Z

Created page with "'''PTIMER''' is a hardware subsystem that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the NV1. It is required to, among other things, f..."

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'''PTIMER''' is a [[hardware subsystem]] that implements a 56-bit programmable interval timer with nanosecond-ish accuracy (it counts in nanoseconds, but cannot be nanosecond accurate due to the clock speed) and controllable speed. It is a foundational component of all Nvidia GPUs and, at least for late 1990s and early 2000s GPU designs, has not changed a huge amount (although some new registers have been added) since the [[NV1]]. It is required to, among other things, for the graphics hardware to perform activities that involve waiting a defined amount of time, for the drivers to know when to poll for GPU state changes and many more things. In order to use the PTIMER CORRECTLY, the <code>PTIMER_NUMERATOR</code> and <code>PTIMER_DENOMINATOR</code> registers must be programmed to appropriate values. Then, the <code>PTIMER_ALARM</code> register must be set in order to set when the alarm is reset. Then, each clock cycle, the <code>PTIMER_TIME_0</code> (bits 31 through 5) and <code>PTIMER_TIME_1</code> (bits 28 through 0) will update based on the number of nanoseconds that have passed. This will occur at a rate set by the result of the calculation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code> (where MCLK is the [[NV3 PRAMDAC|GPU core clock]] on NV3, and [[NV4 PRAMDAC|Memory clock]] on NV4 and later). When <code>PTIMER_TIME_1</code>{{ref|a}} is equal to <code>PTIMER_ALARM</code>, the <code>PTIMER_INTR_ALARM</code> interrupt will be fired and <code>PTIMER_TIME_1</code> will be reset to zero (most likely, <code>PTIMER_TIME_0</code> is incremented at this time). Disabling this interrupt is possible, but extremely unwise: if you are running under nVIDIA's Resource Manager, the drivers will most likely immediately cease to work, since [[NV3 PFIFO|PFIFO]] cache errors will never be caught, some I2C communication and several other critical events will not happen. Interrupts for the PTIMER subsystem cannot be turned off by using [[NV3 PMC|PMC]]'s <code>PMC_INTERRUPT_ENABLE</code> register, nor can PTIMER be turned off using <code>PMC_ENABLE</code>.

== Registers ==

=== PTIMER_INTR (Interrupt Status) ===
* MMIO offset: <code>0x9100</code>
* Available in: NV1+
* Read/write

Displays the current interrupt state for the PTIMER subsystem.

* Bit 0 - <code>PTIMER_INTR_ALARM</code> - If this bit is set, the PTIMER alarm fired. Clear it when the interrupt has been successfully handled.

If bit 0 of <code>PTIMER_INTR_EN</code> is not set, disregard the value of this register.

=== PTIMER_INTR_EN (Interrupt Enable) ===
* MMIO offset: <code>0x9140</code>
* Available in: NV1+
* Read/write

Allows enabling and disabling interrupts for the PTIMER subsystem. In this case, there is only one interrupt to enable.

* Bit 0 - <code>PTIMER_INTR_EN_0_ALARM</code>. Determines if the alarm interrupt is enabled - if this bit is not set, it will not be fired, effectively making this subsystem rather useless.

=== PTIMER_NUMERATOR (Time Count Speed Numerator)===
* MMIO offset: <code>0x9200</code>
* Available in: NV1+
* Read/write

Bits 15 through 0 of this register contain the numerator of the fractional speed that the <code>PTIMER_TIME_1</code> register will increment.

=== PTIMER_DENOMINATOR (Time Count Speed Denominator)===
* MMIO offset: <code>0x9210</code>
* Available in: NV1+
* Read/write

Bits 15 through 0 of this register contain the denominator of the fractional speed that the <code>PTIMER_TIME_1</code> register will increment. Presumably it is a bad idea to set this to zero (although it seems the <code>PTIMER_TIME_1</code> just doesn't count when you do)

=== PTIMER_TIME_0 ===
* MMIO offset: <code>0x9400</code>
* Available in: NV1+
* Read/write

* Bits 31 through 5 of this register contain the high 27 bits of the PTIMER count register. This increments whenever <code>PTIMER_TIME_1</code> rolls over to zero due to overflow.

=== PTIMER_TIME_1 ===
* MMIO offset: <code>0x9410</code>
* Available in: NV1+
* Read/write

* Bits 28 through 0 of this register contain the low 29 bits of the PTIMER count register. This increments every clock cycle by an amount equivalent to the result of the computation <code>MCLK * PTIMER_NUMERATOR / PTIMER_DENOMINATOR</code>, where MCLK is the aforementioned core GPU clock.

=== PTIMER_ALARM ===
* MMIO offset: <code>0x9420</code>
* Available in: NV1+
* Read/write

* Contain the value that <code>PTIMER_TIME_1</code> needs to hold for the <code>PTIMER_INTR_ALARM</code> interrupt to be triggered. There is no way to trigger an interrupt based on the value of <code>PTIMER_TIME_0</code>

=== Notes ===
{{note|a}} The value of <code>PTIMER_TIME_0</code> is not taken into account for the purposes of triggering the alarm interrupt.