NV3 configuration - Revision history

Starfrost at 11:37, 28 August 2025

2025-08-28T11:37:43Z

← Older revision		Revision as of 11:37, 28 August 2025
Line 50:		Line 50:

	{\| class="wikitable"		{\| class="wikitable"
	\|+ ~~Caption text~~		\|+ PFB_BOOT_0 values
	\|-		\|-
	! Bit range (high:low) !! Name !! Purpose !! Values		! Bit range (high:low) !! Name !! Purpose !! Values
	\|-		\|-
	\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~		\| 1:0 \|\| <code>RAM_AMOUNT</code> \|\| The amount of Video RAM on board \|\|
			* 0 = 1 MB (revision A/B) / 8 MB (revision C)
			* 1 = 2 MB
			* 2 = 4 MB

			No 1 MB card was ever made (although earlier drivers mention them, the code was removed at some point), and only a single NEC OEM'd 2 MB card was released (exclusively as an OEM card in Japan)
	\|-		\|-
	\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~		\| 2:2 \|\| <code>RAM_WIDTH</code> \|\| The width of the memory bus \|\|
			* 0 = 64-bit
			* 1 = 128-bit
	\|-		\|-
	\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~		\| 3:3 \|\| <code>RAM_BANKS</code> \|\| The number of banks used for memory. It is not known if one bank corresponds to one physical chip or if the types of RAM chips that are supported are limited. \|\|
			* 0 = 2 banks
			* 1 = 4 banks
	\|-		\|-
	\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~		\| 4:4 \|\| <code>RAMDATA_TWIDDLE</code> \|\| Holds a boolean indicating if the VRAM data should be "twiddled" (possibly some preprocessing required for certain types of RAM chips) \|\|
			* 0 = Off
			* 1 = On
			\|-
			\| 5:5 \|\| <code>RAM_AMOUNT_EXTENSION</code> \|\| Holds a extra bit involving "extension RAM". This most likely exists since <code>RAM_WIDTH</code> 0 indicates 1 megabyte, and it was required in order to distinguish between 1 MB and 8 MB cards. \|\|
			* 0 = None
			* 1 = 8 MB
	\|}		\|}

Starfrost at 12:26, 9 August 2025

2025-08-09T12:26:58Z

← Older revision		Revision as of 12:26, 9 August 2025
Line 45:		Line 45:

	==== PFB_BOOT_0 ====		==== PFB_BOOT_0 ====
			''Main article: [[NV3 PFB#PFB_BOOT_0]]''

	The <code>PFB_BOOT_0</code> provides configuration for the framebuffer interface. It is programmed at board manufacture time, as opposed to chip manufacture time; the configuration information provided by this register is used in order for the graphics chip to communicate with other parts of the hardware, such as the size of the bus, the amount of VRAM connected and the type of VRAM connected to the bus.		The <code>PFB_BOOT_0</code> provides configuration for the framebuffer interface. It is programmed at board manufacture time, as opposed to chip manufacture time; the configuration information provided by this register is used in order for the graphics chip to communicate with other parts of the hardware, such as the size of the bus, the amount of VRAM connected and the type of VRAM connected to the bus.

Starfrost at 12:26, 9 August 2025

2025-08-09T12:26:43Z

← Older revision		Revision as of 12:26, 9 August 2025
Line 2:		Line 2:

	== Configuration types ==		== Configuration types ==

			=== Manufacture-time configuration ===
			Configuration can be done at manufacture time, presumably using chip level modification techniques such as focused ion beam (FIB), by the manufacturer. This kind of configuration encodes both chip-level configuration, such as the stepping, and information required for the graphics chip to communicate with other parts of the hardware, such as the size of the bus, the amount of VRAM connected and the type of VRAM connected to the bus.

			==== PMC_BOOT_0 ====
			''Main article: [[NV3 PMC#PMC_BOOT_0]]''

			{\| class="wikitable"
			\|+ <code>PMC_BOOT_0</code> register bits
			\|-
			! Bit range (high:low) !! Name !! Purpose !! Values
			\|-
			\| 3:0 \|\| <code>FIB_REVISION</code> \|\| Focused ion beam chip modification revision. Presumably for modifying the chip to fix bugs after the die is manufactured \|\|
			* 0 = revision 0
			* 1 = revision 1
			* 2 = revision 2 (NV3T, stepping A03/A04)
			\|-
			\| 7:4 \|\| <code>MASK_REVISION</code> \|\| Revision of the silicon die. \|\|
			* 0 = revision A, RIVA 128 prototype (design finished late January 1997; tapeout March; first prototypes start of April 1997)
			* 1 = revision B, RIVA 128 (already in production by week 33 of 1997)
			* 2 = revision C, RIVA 128 ZX
			\|-
			\| 15:8 \|\| <code>IMPLEMENTATION</code> \|\| Variation of the architecture. This is actually an unused leftover from the NV1 era, where different versions were sold with slightly different functionality (in the case of the NV1, these were the [[NV0]], NV1 with 32-bit DRAM, NV1 with 32-bit VRAM, and an NV1 with a "Picasso" 128-bit DAC), as well as scrapped plans for an audio-less STG-3000 later on. \|\|
			* 0 = NV3
			\|-
			\| 23:16 \|\| <code>ARCHITECTURE</code> \|\| The version of the NV architecture. \|\|
			* 0 = [[NV0]] (never intended to use silicon?)
			* 1 = [[NV1]]
			* 2 = [[NV2]] (cancelled)
			* 3 = [[NV3]]

			In practice only the value 3 will ever be used on NV3.
			\|-
			\| 27:24 \|\| <code>MANUFACTURER</code> \|\| Another NV1 remnant, from when the NV1 could either be branded as the SGS-Thomson STG-2000 (1, <code>MANUFACTURER_SGS</code>) or the Nvidia NV1 (0, <code>MANUFACTURER_NV</code>. \|\|
			* 0 = Nvidia
			\|-
			\| 31:28 \|\| <code>FOUNDRY</code> \|\| The foundry partner that manufactured the GPU. \|\|
			* 0 = SGS-Thomson/STMicroelectronics
			* 1 = Helios
			* 2 = TSMC (NV3T / Riva 128 ZX only)
			\|}

			==== PFB_BOOT_0 ====
			The <code>PFB_BOOT_0</code> provides configuration for the framebuffer interface. It is programmed at board manufacture time, as opposed to chip manufacture time; the configuration information provided by this register is used in order for the graphics chip to communicate with other parts of the hardware, such as the size of the bus, the amount of VRAM connected and the type of VRAM connected to the bus.

			{\| class="wikitable"
			\|+ Caption text
			\|-
			! Bit range (high:low) !! Name !! Purpose !! Values
			\|-
			\| Example \|\| Example \|\| Example \|\| Example
			\|-
			\| Example \|\| Example \|\| Example \|\| Example
			\|-
			\| Example \|\| Example \|\| Example \|\| Example
			\|-
			\| Example \|\| Example \|\| Example \|\| Example
			\|}

			=== Straps (OEM or VBIOS-level configuration) ===

			=== BIOS command system ===

Starfrost at 18:52, 7 August 2025

2025-08-07T18:52:20Z

← Older revision		Revision as of 18:52, 7 August 2025
Line 1:		Line 1:
	There are several different ways that an NV3-based GPU can be configured, depending on the level of flexibility required and who is configuring it. Configuration is done at either the OEM card design level, the manufacture time of the chip, or at the VBIOS or driver level. Each of these have their own mechanisms for configuration; some appear to be burned in with a focused ion beam (FIB)-type ~~situation~~, others use physical solder-bridged jumpers or other similar mechanisms at the board level, and others are done via software. In some cases, multiple of these methods are usable.		There are several different ways that an NV3-based GPU can be configured, depending on the level of flexibility required and who is configuring it. Configuration is done at either the OEM card design level, the manufacture time of the chip, or at the VBIOS or driver level. Each of these have their own mechanisms for configuration; some appear to be burned into the silicon with a focused ion beam (FIB)-type technique, others use physical solder-bridged jumpers or other similar mechanisms at the board level, and others are done via software. In some cases, multiple of these methods are usable.

	== Configuration types ==		== Configuration types ==

Starfrost: Created page with "There are several different ways that an NV3-based GPU can be configured, depending on the level of flexibility required and who is configuring it. Configuration is done at either the OEM card design level, the manufacture time of the chip, or at the VBIOS or driver level. Each of these have their own mechanisms for configuration; some appear to be burned in with a focused ion beam (FIB)-type situation, others use physical solder-bridged jumpers or other similar mechanis..."

2025-08-07T18:52:06Z

Created page with "There are several different ways that an NV3-based GPU can be configured, depending on the level of flexibility required and who is configuring it. Configuration is done at either the OEM card design level, the manufacture time of the chip, or at the VBIOS or driver level. Each of these have their own mechanisms for configuration; some appear to be burned in with a focused ion beam (FIB)-type situation, others use physical solder-bridged jumpers or other similar mechanis..."

New page

There are several different ways that an NV3-based GPU can be configured, depending on the level of flexibility required and who is configuring it. Configuration is done at either the OEM card design level, the manufacture time of the chip, or at the VBIOS or driver level. Each of these have their own mechanisms for configuration; some appear to be burned in with a focused ion beam (FIB)-type situation, others use physical solder-bridged jumpers or other similar mechanisms at the board level, and others are done via software. In some cases, multiple of these methods are usable.

== Configuration types ==