NV1 object classes - Revision history

Starfrost: im stupid

2025-10-23T00:13:27Z

im stupid

← Older revision		Revision as of 00:13, 23 October 2025
Line 8:		Line 8:

	=== <code>UBETA</code> (0x01 / 0x40) ===		=== <code>UBETA</code> (0x01 / 0x40) ===
	=== UROP (0x02 / 0x41) ===		=== <code>UROP</code> (0x02 / 0x41) ===
	=== UCHROMA (0x03 / 0x43) ===		=== <code>UCHROMA</code> (0x03 / 0x43) ===
	=== UPLANE (0x04 / 0x44) ===		=== <code>UPLANE</code> (0x04 / 0x44) ===
	=== UCLIP (0x05 / 0x45) ===		=== <code>UCLIP</code> (0x05 / 0x45) ===
	=== UPATT (0x06 / 0x46) ===		=== <code>UPATT</code> (0x06 / 0x46) ===
	=== UPOINT (0x08 / 0x48) ===		=== <code>UPOINT</code> (0x08 / 0x48) ===
	=== ULINE (0x09 / 0x49) ===		=== <code>ULINE</code> (0x09 / 0x49) ===
	=== ULIN (0x0A / 0x4A) ===		=== <code>ULIN</code> (0x0A / 0x4A) ===
	=== UTRI (0x0B / 0x4B) ===		=== <code>UTRI</code> (0x0B / 0x4B) ===
	=== URECT (0x0C / 0x4C) ===		=== <code>URECT</code> (0x0C / 0x4C) ===
	=== UBTM (0x0D / 0x4D) ===		=== <code>UBTM </code>(0x0D / 0x4D) ===
	=== UQTM (0x0E / 0x4E) ===		=== <code>UQTM</code> (0x0E / 0x4E) ===
	=== UBLIT (0x10 / 0x50) ===		=== <code>UBLIT</code> (0x10 / 0x50) ===
	=== UIMAGE (0x11 / 0x51) ===		=== <code>UIMAGE</code> (0x11 / 0x51) ===
	=== UBITMAP (0x12 / 0x52) ===		=== <code>UBITMAP</code> (0x12 / 0x52) ===
	=== UFROMEM (0x13 / 0x53) ===		=== <code>UFROMEM</code> (0x13 / 0x53) ===
	=== UTOMEM (0x14 / 0x54) ===		=== <code>UTOMEM</code> (0x14 / 0x54) ===
	=== UBTMB (0x1D / 0x5D) ===		=== <code>UBTMB</code> (0x1D / 0x5D) ===
	=== UQTMB (0x1E / 0x5E) ===		=== <code>UQTMB</code> (0x1E / 0x5E) ===

Starfrost at 00:12, 23 October 2025

2025-10-23T00:12:24Z

← Older revision		Revision as of 00:12, 23 October 2025
Line 7:		Line 7:
	It appears that PIO subchannels get mapped to write-only registers at <code>(0x400000 + (0x10000 * class_id))</code> in MMIO - e.g. UBETA is at <code>0x410000</code>.		It appears that PIO subchannels get mapped to write-only registers at <code>(0x400000 + (0x10000 * class_id))</code> in MMIO - e.g. UBETA is at <code>0x410000</code>.

	=== UBETA (0x01 / 0x40) ===		=== <code>UBETA</code> (0x01 / 0x40) ===
	=== UROP (0x02 / 0x41) ===		=== UROP (0x02 / 0x41) ===
	=== UCHROMA (0x03 / 0x43) ===		=== UCHROMA (0x03 / 0x43) ===

Starfrost at 00:12, 23 October 2025

2025-10-23T00:12:15Z

← Older revision		Revision as of 00:12, 23 October 2025
Line 5:		Line 5:
	Objects must first be submitted (see [[NV1 Object Submission]] and [[NV1 PFIFO]]). As many methods can be submitted as possible (methods are defined as offsets within the PIO subchannel allocated to the object), but methods need to be submitted in the right order for rendering to occur. There is no mapping between the number of objects rendered and the number of objects submiteted		Objects must first be submitted (see [[NV1 Object Submission]] and [[NV1 PFIFO]]). As many methods can be submitted as possible (methods are defined as offsets within the PIO subchannel allocated to the object), but methods need to be submitted in the right order for rendering to occur. There is no mapping between the number of objects rendered and the number of objects submiteted

	It appears that PIO subchannels get mapped to write-only registers at <code>(0x400000 + (0x10000 * class_id))</code> in MMIO - e.g. UBETA is at <code>0x410000</code.		It appears that PIO subchannels get mapped to write-only registers at <code>(0x400000 + (0x10000 * class_id))</code> in MMIO - e.g. UBETA is at <code>0x410000</code>.

	=== UBETA (0x01 / 0x40) ===		=== UBETA (0x01 / 0x40) ===

Starfrost at 00:12, 23 October 2025

2025-10-23T00:12:04Z

← Older revision		Revision as of 00:12, 23 October 2025
Line 7:		Line 7:
	It appears that PIO subchannels get mapped to write-only registers at <code>(0x400000 + (0x10000 * class_id))</code> in MMIO - e.g. UBETA is at <code>0x410000</code.		It appears that PIO subchannels get mapped to write-only registers at <code>(0x400000 + (0x10000 * class_id))</code> in MMIO - e.g. UBETA is at <code>0x410000</code.

	=== ~~<pre>~~UBETA~~</pre>~~ (0x01 / 0x40) ===		=== UBETA (0x01 / 0x40) ===
	=== ~~<code>~~UROP~~</code>~~ (0x02 / 0x41) ===		=== UROP (0x02 / 0x41) ===
	=== ~~<code>~~UCHROMA~~</code>~~ (0x03 / 0x43) ===		=== UCHROMA (0x03 / 0x43) ===
	=== ~~<code>~~UPLANE~~</code>~~ (0x04 / 0x44) ===		=== UPLANE (0x04 / 0x44) ===
	=== ~~<code>~~UCLIP~~</code>~~ (0x05 / 0x45) ===		=== UCLIP (0x05 / 0x45) ===
	=== ~~<code>~~UPATT~~</code>~~ (0x06 / 0x46) ===		=== UPATT (0x06 / 0x46) ===
	=== ~~<code>~~UPOINT~~</code>~~ (0x08 / 0x48) ===		=== UPOINT (0x08 / 0x48) ===
	=== ~~<code>~~ULINE~~</code>~~ (0x09 / 0x49) ===		=== ULINE (0x09 / 0x49) ===
	=== ~~<code>~~ULIN~~</code>~~ (0x0A / 0x4A) ===		=== ULIN (0x0A / 0x4A) ===
	=== ~~<code>~~UTRI~~</code>~~ (0x0B / 0x4B) ===		=== UTRI (0x0B / 0x4B) ===
	=== ~~<code>~~URECT~~</code>~~ (0x0C / 0x4C) ===		=== URECT (0x0C / 0x4C) ===
	=== ~~<code>~~UBTM~~</code>~~ (0x0D / 0x4D) ===		=== UBTM (0x0D / 0x4D) ===
	=== ~~<code>~~UQTM~~</code>~~ (0x0E / 0x4E) ===		=== UQTM (0x0E / 0x4E) ===
	=== ~~<code>~~UBLIT~~</code>~~ (0x10 / 0x50) ===		=== UBLIT (0x10 / 0x50) ===
	=== ~~<code>~~UIMAGE~~</code>~~ (0x11 / 0x51) ===		=== UIMAGE (0x11 / 0x51) ===
	=== ~~<code>~~UBITMAP~~</code>~~ (0x12 / 0x52) ===		=== UBITMAP (0x12 / 0x52) ===
	=== ~~<code>~~UFROMEM~~</code>~~ (0x13 / 0x53) ===		=== UFROMEM (0x13 / 0x53) ===
	=== ~~<code>~~UTOMEM~~</code>~~ (0x14 / 0x54) ===		=== UTOMEM (0x14 / 0x54) ===
	=== ~~<code>~~UBTMB~~</code>~~ (0x1D / 0x5D) ===		=== UBTMB (0x1D / 0x5D) ===
	=== ~~<code>~~UQTMB~~</code>~~ (0x1E / 0x5E) ===		=== UQTMB (0x1E / 0x5E) ===

Starfrost: Created page with "This is the list of '''object classes''' that can be submitted via PFIFO on NV1. '''Note:''' This is the internal class interface. The Resource Manager provides a different class interface before NV4. These are the class IDs required to actually submit objects to the GPU hardware - the IDs must be shifted right by 12 bits to be submitted (in effect, they show up as `0x40-0x5F` while viewing RAMHT in a hex editor, like on NV3) Object..."

2025-10-23T00:10:49Z

Created page with "This is the list of '''object classes''' that can be submitted via PFIFO on NV1. '''Note:''' This is the internal class interface. The Resource Manager provides a different class interface before NV4. These are the class IDs required to actually submit objects to the GPU hardware - the IDs must be shifted right by 12 bits to be submitted (in effect, they show up as <code>0x40-0x5F</code> while viewing RAMHT in a hex editor, like on NV3) Object..."

New page

This is the list of '''object classes''' that can be submitted via PFIFO on [[NV1]].

'''Note:''' This is the internal class interface. The Resource Manager provides a different class interface before [[NV4]]. These are the class IDs required to actually submit objects to the GPU hardware - the IDs must be shifted right by 12 bits to be submitted (in effect, they show up as <code>0x40-0x5F</code> while viewing [[NV1 RAMHT|RAMHT]] in a hex editor, like on [[NV3]])

Objects must first be submitted (see [[NV1 Object Submission]] and [[NV1 PFIFO]]). As many methods can be submitted as possible (methods are defined as offsets within the PIO subchannel allocated to the object), but methods need to be submitted in the right order for rendering to occur. There is no mapping between the number of objects rendered and the number of objects submiteted

It appears that PIO subchannels get mapped to write-only registers at <code>(0x400000 + (0x10000 * class_id))</code> in MMIO - e.g. UBETA is at <code>0x410000</code.

=== <pre>UBETA</pre> (0x01 / 0x40) ===
=== <code>UROP</code> (0x02 / 0x41) ===
=== <code>UCHROMA</code> (0x03 / 0x43) ===
=== <code>UPLANE</code> (0x04 / 0x44) ===
=== <code>UCLIP</code> (0x05 / 0x45) ===
=== <code>UPATT</code> (0x06 / 0x46) ===
=== <code>UPOINT</code> (0x08 / 0x48) ===
=== <code>ULINE</code> (0x09 / 0x49) ===
=== <code>ULIN</code> (0x0A / 0x4A) ===
=== <code>UTRI</code> (0x0B / 0x4B) ===
=== <code>URECT</code> (0x0C / 0x4C) ===
=== <code>UBTM</code> (0x0D / 0x4D) ===
=== <code>UQTM</code> (0x0E / 0x4E) ===
=== <code>UBLIT</code> (0x10 / 0x50) ===
=== <code>UIMAGE</code> (0x11 / 0x51) ===
=== <code>UBITMAP</code> (0x12 / 0x52) ===
=== <code>UFROMEM</code> (0x13 / 0x53) ===
=== <code>UTOMEM</code> (0x14 / 0x54) ===
=== <code>UBTMB</code> (0x1D / 0x5D) ===
=== <code>UQTMB</code> (0x1E / 0x5E) ===