NV1 RMC - Revision history

Starfrost at 00:47, 26 December 2025

2025-12-26T00:47:55Z

← Older revision		Revision as of 00:47, 26 December 2025
Line 8:		Line 8:
	2. Configure the windowing information (i.e. what 8KB range of MMIO you want your three sliding windows to point to) by writing <code>start position of window >> 13 bits</code> to <code>B1E40</code>. For unknown reasons, there is a separate windowing system for SVGA VRAM, which allows the user to map anywhere in the real-mode address space (1 MB) in 8KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]] core), the SVGA legacy VRAM is simply directly mapped into BAR0 at <code>0xA0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off-the-shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8KB range of MMIO you want your three sliding windows to point to) by writing <code>start position of window >> 13 bits</code> to <code>B1E40</code>. For unknown reasons, there is a separate windowing system for SVGA VRAM, which allows the user to map anywhere in the real-mode address space (1 MB) in 8KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]] core), the SVGA legacy VRAM is simply directly mapped into BAR0 at <code>0xA0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off-the-shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing to the region from <code>0xB2000</code> to <code>0xB4000</code>, which will map to the first 8KB VGA window. Add <code>0x2000</code> for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32MB of ~~MIO~~ space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24KB (8KB per window and a maximum of three windows) can be accessed at any given time.		3. Do I/O by writing to the region from <code>0xB2000</code> to <code>0xB4000</code>, which will map to the first 8KB VGA window. Add <code>0x2000</code> for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32MB of M.IO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24KB (8KB per window and a maximum of three windows) can be accessed at any given time.

	4. When you are done, write <code>NoNV</code> to <code>0xB1E10</code>, so that VGA VRAM is accessible again.		4. When you are done, write <code>NoNV</code> to <code>0xB1E10</code>, so that VGA VRAM is accessible again.

Huanker: Forgot to capitalize M.

2025-12-25T20:44:50Z

Forgot to capitalize M.

← Older revision		Revision as of 20:44, 25 December 2025
Line 1:		Line 1:
	Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons, the video BIOS has to run in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sitting on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-~~mode~~ Access]] subsystem.		Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons, the video BIOS has to run in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sitting on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-Mode Access]] subsystem.

	The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals, up to 32760KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>0xB1400</code>, with the 8KB window starting at <code>0xB2000</code>), therefore they have to allow this system to be transparently turned on and off. The regular GPU can access the RMC registers using the following formula: <code>0x1400 + (addr & 0xFF)</code>; an example of this would be accessing the window settings at BAR0 <code>0x1400</code>.		The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals, up to 32760KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>0xB1400</code>, with the 8KB window starting at <code>0xB2000</code>), therefore they have to allow this system to be transparently turned on and off. The regular GPU can access the RMC registers using the following formula: <code>0x1400 + (addr & 0xFF)</code>; an example of this would be accessing the window settings at BAR0 <code>0x1400</code>.

Huanker: Cleaned up some of the page syntax.

2025-12-25T20:43:55Z

Cleaned up some of the page syntax.

← Older revision		Revision as of 20:43, 25 December 2025
Line 1:		Line 1:
	Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run ~~code~~ in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is ~~sittig~~ on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access]] subsystem. The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to ~~32760 KB~~. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>~~B1400~~</code>, with the 8KB window starting at <code>~~B2000~~</code>), therefore they have to allow this system to be transparently turned off ~~and on~~. The regular GPU can access the RMC registers using the following formula: (<code>0x1400 + (addr & 0xFF)</code>); an example of this would be accessing the window settings at BAR0 <code>0x1400</code>m		Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons, the video BIOS has to run in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sitting on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access]] subsystem.

			The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals, up to 32760KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>0xB1400</code>, with the 8KB window starting at <code>0xB2000</code>), therefore they have to allow this system to be transparently turned on and off. The regular GPU can access the RMC registers using the following formula: <code>0x1400 + (addr & 0xFF)</code>; an example of this would be accessing the window settings at BAR0 <code>0x1400</code>.

	== How to Use ==		== How to Use ==
	1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>.		1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>.

	2. Configure the windowing information (i.e. what ~~8kb~~ range of MMIO you want your three sliding windows to point to) by writing (start position of window >> 13 bits) to <code>B1E40</code>. For unknown reasons, there is a separate windowing system for SVGA VRAM ~~for some reason~~, which allows the user to map anywhere in the real-mode address space (1 MB) in ~~8 KB~~ blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is ~~imply~~ directly mapped into BAR0 at <code>~~A0000~~</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8KB range of MMIO you want your three sliding windows to point to) by writing <code>start position of window >> 13 bits</code> to <code>B1E40</code>. For unknown reasons, there is a separate windowing system for SVGA VRAM, which allows the user to map anywhere in the real-mode address space (1 MB) in 8KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]] core), the SVGA legacy VRAM is simply directly mapped into BAR0 at <code>0xA0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off-the-shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing to the region from <code>B2000</code> to <code>B4000</code>, which will map to the first 8192 byte VGA window. Add 0x2000 for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.

	~~4. When you are done write <code>NoNV</code> to <code>0xB1E10</code>, so that VGA VRAM is accessible again~~.

	~~The RMC mechanism internally works using DMA~~. ~~The DMA settings can be changed via manipulating~~ the ~~value of~~ the <code>~~NV_PBUS_RMC_DMA_0~~</code> ~~register~~. ~~A example~~ of ~~this~~ would be ~~changing the direction by flipping bit 26~~ and ~~changing the tarhget DMA address by overwriting bits 23 through 0~~.		3. Do I/O by writing to the region from <code>0xB2000</code> to <code>0xB4000</code>, which will map to the first 8KB VGA window. Add <code>0x2000</code> for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24KB (8KB per window and a maximum of three windows) can be accessed at any given time.

			4. When you are done, write <code>NoNV</code> to <code>0xB1E10</code>, so that VGA VRAM is accessible again.

			The RMC mechanism internally works using DMA. The DMA settings can be changed via manipulating the value of the <code>NV_PBUS_RMC_DMA_0</code> register. A example of this would be changing the direction by flipping bit 26 and changing the target DMA address by overwriting bits 23 through 0.

	== Register Reference ==		== Register Reference ==

Starfrost at 18:40, 25 December 2025

2025-12-25T18:40:52Z

← Older revision		Revision as of 18:40, 25 December 2025
Line 1:		Line 1:
	Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access]] subsystem. The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760 KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be accessing the window settings at BAR0 <code>0x1400</code>m		Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access]] subsystem. The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760 KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using the following formula: (<code>0x1400 + (addr & 0xFF)</code>); an example of this would be accessing the window settings at BAR0 <code>0x1400</code>m

	== How to Use ==		== How to Use ==
	1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code> .		1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>.

	2. Configure the windowing information (i.e. what 8kb range of MMIO you want your three sliding windows to point to) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8kb range of MMIO you want your three sliding windows to point to) by writing (start position of window >> 13 bits) to <code>B1E40</code>. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing to the region from <code>B2000</code> to <code>B4000</code>, which will map to the first 8192 byte VGA window. Add 0x2000 for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.		3. Do I/O by writing to the region from <code>B2000</code> to <code>B4000</code>, which will map to the first 8192 byte VGA window. Add 0x2000 for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.

	4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again.		4. When you are done write <code>NoNV</code> to <code>0xB1E10</code>, so that VGA VRAM is accessible again.

	The RMC mechanism internally works using DMA. The DMA settings can be changed via manipulating the value of the <code>NV_PBUS_RMC_DMA_0</code> register. A example of this would be changing the direction by flipping bit 26 and changing the tarhget DMA address by overwriting bits 23 through 0.		The RMC mechanism internally works using DMA. The DMA settings can be changed via manipulating the value of the <code>NV_PBUS_RMC_DMA_0</code> register. A example of this would be changing the direction by flipping bit 26 and changing the tarhget DMA address by overwriting bits 23 through 0.

Starfrost at 14:17, 25 December 2025

2025-12-25T14:17:14Z

← Older revision		Revision as of 14:17, 25 December 2025
Line 6:		Line 6:
	2. Configure the windowing information (i.e. what 8kb range of MMIO you want your three sliding windows to point to) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8kb range of MMIO you want your three sliding windows to point to) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing from B2000.~~..B4000~~. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.		3. Do I/O by writing to the region from <code>B2000</code> to <code>B4000</code>, which will map to the first 8192 byte VGA window. Add 0x2000 for each window after the first. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.

	4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again.		4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again.

Starfrost at 14:11, 25 December 2025

2025-12-25T14:11:41Z

← Older revision		Revision as of 14:11, 25 December 2025
Line 4:		Line 4:
	1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code> .		1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code> .

	2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to ~~look at~~) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8kb range of MMIO you want your three sliding windows to point to) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.		3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.

Starfrost at 14:11, 25 December 2025

2025-12-25T14:11:22Z

← Older revision		Revision as of 14:11, 25 December 2025
Line 1:		Line 1:
	Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access] subsystem. The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760 KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be accessing the window settings at BAR0 <code>0x1400</code>m		Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access]] subsystem. The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760 KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be accessing the window settings at BAR0 <code>0x1400</code>m

	== How to Use ==		== How to Use ==

Starfrost at 14:11, 25 December 2025

2025-12-25T14:11:13Z

← Older revision		Revision as of 14:11, 25 December 2025
Line 1:		Line 1:
	Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access] subsystem.		Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] (and in any future [[Weitek]] VGA Nvidia cards) this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access] subsystem. The VBIOS is exposed to the "real" GPU MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760 KB. For unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be accessing the window settings at BAR0 <code>0x1400</code>m

	The VBIOS is exposed to MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to ~~32760kb~~. ~~HFor~~ unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be ~~accssing~~ the window settings at BAR0 <code>0x1400</code>

	== How to Use ==		== How to Use ==
	1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>		1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code> .

	2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use		3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use since only 24 KB (8 KB per window and a maximum of three windows) can be accessed at any given time.

	4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again.		4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again.

Starfrost at 14:10, 25 December 2025

2025-12-25T14:10:06Z

← Older revision		Revision as of 14:10, 25 December 2025
Line 6:		Line 6:
	1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>		1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>

	2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. ~~There~~ is a separate windowing system for SVGA VRAM for some reason which allows ~~you~~ to map 0-~~>1mb~~ in ~~8kb~~ blocks and has an additional feature where bit 12 toggles linear mappings or VGA bitplane mapping. ~~This~~ is ~~odd~~, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. For unknown reasons, there is a separate windowing system for SVGA VRAM for some reason, which allows the user to map anywhere in the real-mode address space (1 MB) in 8 KB blocks, and has an additional feature where bit 12 toggles two different modes - standard linear mappings or VGA bitplane style mapping. The existence of this system is rather strange, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use		3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use

Starfrost at 14:09, 25 December 2025

2025-12-25T14:09:16Z

← Older revision		Revision as of 14:09, 25 December 2025
Line 1:		Line 1:
	Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access] subsystem.		Like all VGA compatible video controllers, the Nvidia NV1 has a Video BIOS. However, for legacy compatibility reasons the video BIOS has to run code in 16-bit real mode and is not aware of the bus (either VLB or PCI) that it is sittig on. By default, without special dispensations, the graphics card will not be able to write to the MMIO of the GPU, which is mapped as PCI BAR0. In [[NV3]] this system was replaced by the much simpler [[NV3 RMA\|Real-mode Access] subsystem.

	The VBIOS is exposed to MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760kb. HFor unknown reasons, the registers for this functionality have been to put the registers for this in VRAM (e.g. the window settings are at `B1400`, ~~mirrored to `0x1440` in BAR0, and~~ the 8KB window ~~starts~~ at `B2000`), therefore they have to allow this system to be transparently turned off and on. ~~So these are~~ the ~~steps~~:		The VBIOS is exposed to MMIO via an extremely overengineered system of 3 sliding windows of up to 8KB in size, using a segment system that can move them anywhere in the NV1's 32MB MMIO space in 8KB intervals up to 32760kb. HFor unknown reasons, the registers for this functionality have been to put the registers for this ''in VGA VRAM'' (e.g. the window settings are at <code>B1400</code>, with the 8KB window starting at <code>B2000</code>), therefore they have to allow this system to be transparently turned off and on. The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`); an example of this would be accssing the window settings at BAR0 <code>0x1400</code>

	== How to Use ==		== How to Use ==
	1. Write 4 ~~chars `~~GoNV` to `0xB1E10`		1. Write the 4 characters <code>GoNV</code> to <code>0xB1E10</code>

	2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. There is a separate windowing system for SVGA VRAM for some reason which allows you to map 0->1mb in 8kb blocks and has an additional feature where bit 12 toggles linear mappings or VGA bitplane mapping. This is odd, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.		2. Configure the windowing information (i.e. what 8kb range of MMIO you want your 3 sliding windows to look at) by writing (start position of window >> 13 bits) to `B1E40`. There is a separate windowing system for SVGA VRAM for some reason which allows you to map 0->1mb in 8kb blocks and has an additional feature where bit 12 toggles linear mappings or VGA bitplane mapping. This is odd, because in later Nvidia GPUs (those that use the [[Weitek]]] core), the SVGA legacy VRAM is imply directly mapped into BAR0 at <code>A0000</code>, but I don't know if it is here yet. If it is not, using this method to access VGA VRAM from the main GPU would be a requirement. There is circumstantial evidence in favour of this eventuality, since the VGA in the NV1 is a separate PCI function and is likely an off the shelf STMicroelectronics VGA core combined with software emulation.

	3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use		3. Do I/O by writing from B2000...B4000. This is not as useful as it initially seems, since all NV1 registers are 32-bit and the registers are extremely spaced out within the 32 MB of MIO space. However, accessing the real VRAM is possible by writing from 16MB onwards, although it would be extremely cumbersome to use
	~~4. When you are done write `NoNV` to `0xB1E10` so you can actually use VGA VRAM again~~

	~~This~~ internally works by using DMA. The DMA settings can be changed via manipulating the value of the <code>NV_PBUS_RMC_DMA_0</code> register. A example of this would be changing the direction by flipping bit 26 and changing the tarhget DMA address by overwriting bits 23 through 0.		4. When you are done write `NoNV` to `0xB1E10`, so that VGA VRAM is accessible again.

			The RMC mechanism internally works using DMA. The DMA settings can be changed via manipulating the value of the <code>NV_PBUS_RMC_DMA_0</code> register. A example of this would be changing the direction by flipping bit 26 and changing the tarhget DMA address by overwriting bits 23 through 0.


	~~The regular GPU can access the RMC registers using: (`0x1400 + (addr & 0xFF)`~~

	== ~~Registers~~ ==		== Register Reference ==