List of GPUs - Revision history

Starfrost at 01:54, 31 December 2025

2025-12-31T01:54:20Z

← Older revision		Revision as of 01:54, 31 December 2025
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	=== NV4 (RIVA TNT) ===		=== NV4 (RIVA TNT) ===
	By April of 1997, revenues were soaring and the future of the company was secured. Therefore, nVIDIA began work on their next generation design, which would have enough time in the oven to be polished and finished on release; large refactors of both the hardware and software platforms used since [[NV1]] were undertaken. Due to this (the NV4 is the first GPU supported by modern-style multi-chip drivers, rather than requiring a separate Resource Manager branch for every single model of hardware), for a very long time (until just before the debut of CUDA) this design was considered to be the "base" level that all other designs extended, with newer GPUs being "NV4 compatible". Despite having to be underclocked quite severely, it was still almost as fast as the Voodoo2 with several serious advantages		By April of 1997, revenues were soaring and the future of the company was secured. Therefore, nVIDIA began work on their next generation design, which would have enough time in the oven to be polished and finished on release; large refactors of both the hardware and software platforms used since [[NV1]] were undertaken. Due to this (the NV4 is the first GPU supported by modern-style multi-chip drivers, rather than requiring a separate Resource Manager branch for every single model of hardware), for a very long time (until just before the debut of CUDA) this design was considered to be the "base" level that all other designs extended, with newer GPUs being "NV4 compatible". Despite having to be underclocked quite severely, it was still almost as fast as the Voodoo2 with several serious advantages; the GPU was released as the RIVA TNT in August 1998 and, despite some controversy over its underclocking, sold and reviewed very well.

	====Added features====		====Added features====

Starfrost at 01:46, 31 December 2025

2025-12-31T01:46:36Z

← Older revision		Revision as of 01:46, 31 December 2025
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	* [[Weitek]] CRTC extended sequencer register locking was moved from sequencer register 0x6 to CRTC register 0x1F		* [[Weitek]] CRTC extended sequencer register locking was moved from sequencer register 0x6 to CRTC register 0x1F
	** CRTC extended sequencer registers can be unlocked for read or both read and write. In NV3 they can only be unlocked for read and write		** CRTC extended sequencer registers can be unlocked for read or both read and write. In NV3 they can only be unlocked for read and write
			* <code>PRAMDAC</code> can output 24 bit colour - the GPU still only works with 8, 16 and 32 bit colour, and it doesn't seem these modes are exposed to the display drivers.

	====Removed features====		====Removed features====
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	* PC-98 support		* PC-98 support
	* Microsoft zero-order hold texture (<code>ZOH_MS</code>) coordinate interpolation		* Microsoft zero-order hold texture (<code>ZOH_MS</code>) coordinate interpolation
			* <code>PRAMDAC_GENERAL_CONTROL_565_MODE</code> is removed, replaced with the <code>ALT_MODE</code> bit, which can cause 16bpp to become 15bpp and 32bpp to become 24bpp

	=== NV5 (RIVA TNT2) ===		=== NV5 (RIVA TNT2) ===

Starfrost at 01:43, 31 December 2025

2025-12-31T01:43:41Z

← Older revision		Revision as of 01:43, 31 December 2025
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	* 3D capability at resolutions above 960*720 is possible again		* 3D capability at resolutions above 960*720 is possible again
	* The ability to write to <code>PSTRAPS</code>		* The ability to write to <code>PSTRAPS</code>
	* ACPI support (indicated by the PCI device ID changing to <code>0x0019/code>)		* ACPI support (indicated by the PCI device ID changing to <code>0x0019</code>)
	* Notifiers to VRAM rather than just the main system RAM (check this)		* Notifiers to VRAM rather than just the main system RAM (check this)
	* Higher RAMDAC clock (260Mhz instead of 205)		* Higher RAMDAC clock (260Mhz instead of 205)

Starfrost at 01:43, 31 December 2025

2025-12-31T01:43:03Z

← Older revision		Revision as of 01:43, 31 December 2025
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	* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)		* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)
	* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit		* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit
	* The ability to scale and stretch images while receiving them from system memory (`USCALED` and `USTRTCH` objects)		* The ability to scale and stretch images while receiving them from system memory (<code>USCALED</code> and <code>USTRTCH</code> objects)
	* Generic image upload objects		* Generic image upload objects
	* AGP 1X bus support		* AGP 1X bus support
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	* Hardware-accelerated color space conversion		* Hardware-accelerated color space conversion
	* Hardware cursor now supports colour		* Hardware cursor now supports colour
			* Configurable frustum culling modes (clockwise/counterclockwise)
	* YUV420 and YUV422 support		* YUV420 and YUV422 support
	* PC-98 support ("NEC mode")		* PC-98 support changed to "NEC mode" strap rather than different VBIOS
	* Moved to a new 350 nm process rather than 500 nm		* Moved to a new 350 nm process rather than 500 nm
	* "Mediaport" on-card that allows plugging in external MPEG decoder		* "Mediaport" on-card that allows plugging in external MPEG decoder
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	* 1080p and 1920x1200 resolution support in the BIOS		* 1080p and 1920x1200 resolution support in the BIOS
	* PFIFO CACHE1 is now 64 slots deep instead of 32		* PFIFO CACHE1 is now 64 slots deep instead of 32
	* 3D capability at resolutions above 960*720 is ~~better~~ again		* 3D capability at resolutions above 960*720 is possible again
	* The ability to write to `PSTRAPS`		* The ability to write to <code>PSTRAPS</code>
	* ACPI support (indicated by the PCI device ID changing to `0x0019`)		* ACPI support (indicated by the PCI device ID changing to <code>0x0019/code>)
	* Notifiers to VRAM rather than just the main system RAM (check this)		* Notifiers to VRAM rather than just the main system RAM (check this)
	* Higher RAMDAC clock (260Mhz instead of 205)		* Higher RAMDAC clock (260Mhz instead of 205)
	* Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)		** Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)
	* AGP 2X bus support		* AGP 2X bus support

	=== NV4 (RIVA TNT) ===		=== NV4 (RIVA TNT) ===
			By April of 1997, revenues were soaring and the future of the company was secured. Therefore, nVIDIA began work on their next generation design, which would have enough time in the oven to be polished and finished on release; large refactors of both the hardware and software platforms used since [[NV1]] were undertaken. Due to this (the NV4 is the first GPU supported by modern-style multi-chip drivers, rather than requiring a separate Resource Manager branch for every single model of hardware), for a very long time (until just before the debut of CUDA) this design was considered to be the "base" level that all other designs extended, with newer GPUs being "NV4 compatible". Despite having to be underclocked quite severely, it was still almost as fast as the Voodoo2 with several serious advantages

			====Added features====
			* Up to 16 MB VRAM
			* Hardware-accelerated stencil buffering (8-bit); can be interlaced with the Z buffer for higher performance and lower memory bandwidth use ("zeta buffer")
			* 16 DMA channels instead of 8
			* Pushbuffer-based DMA object submission
			** They can be 124 or 512 bytes
			* 32-bit 3D rendering
			* Dual texture pipes that can rasterise two texels per cycle
			* PFIFO CACHE1 is now 128 slots deep instead of 64
			* Class system in GPU is now the same as the class system in the Resource Manager
			* FIFO timeslice scheduler
			* [[NV4 PGRAPH#Colour combiners\|Colour combiners]], two proto-shaders that operate on the fragments right before rasterisation - the result of one can be passed into the other.
			* Unified memory support for iGPUs
			* Some DVD acceleration support (such as support for various DVD colour formats like <code>A4V6YB6A4U6YA6</code>), but I am not sure if it was finished
			* Trilinear filtering
			* Anisotropic filtering (kind of crappy and approximated)
			* Texture swizzling
			* Configurable Z buffer format (IEEE 754 float or fixed point)
			* Up to 6 buffers
			** Ability to swizzle buffers 2 and 5
			** Buffers are now optionally part of the MMU with a base and limit
			* Somewhat different <code>NvNotification</code> format
			* Ability to scramble the framebuffer
			* MMIO register to change start of CRTC VGA framebuffer
			* Even more debug registers, including ping-pong mode (what??)
			* An extremely basic two instruction set DMA bytecode to allow jumping between different parts of DMA streams
			* 16bpp modes are now actually 16bpp by default, not 15bpp
			* Buffer formats <code>Z8R8G8B8</code>, <code>O1Z7R8G8B8</code> and <code>O1A7R8G8B8</code> for interlacing Z and colour buffers
			* YUV buffer formats <code>V8YB8U8YA8</code> and <code>YB8V8YA8U8</code>
			* <code>FFINTFC</code> registers for internal state information
			* [[Weitek]] CRTC extended sequencer register locking was moved from sequencer register 0x6 to CRTC register 0x1F
			** CRTC extended sequencer registers can be unlocked for read or both read and write. In NV3 they can only be unlocked for read and write

	* ~~Hardware~~-~~accelerated stencil buffering~~		====Removed features====
			* 1 MB VRAM (2 and 4 are actually supported but none were ever made, although 4 MB was announced)
			* <code>U*</code> registers. Instead, method information can be obtained via determining which Resource Manager methods are sent to hardware.
			* [[NV3 DMA]] mode submission
			* PC-98 support
			* Microsoft zero-order hold texture (<code>ZOH_MS</code>) coordinate interpolation

	=== NV5 (RIVA TNT2) ===		=== NV5 (RIVA TNT2) ===

Starfrost at 14:59, 27 December 2025

2025-12-27T14:59:12Z

← Older revision		Revision as of 14:59, 27 December 2025
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	This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) ~~sometimes made~~ dozens of ~~mdoels~~ for a particular "series" and the list would be full of hundreds of almost identical ~~SKUs~~.		This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) often produced dozens of SKUs for a particular "series" and the list would be full of hundreds of almost identical graphics cards.

	==Quadratic texture mappers==		==Quadratic texture mappers==

Starfrost at 14:58, 27 December 2025

2025-12-27T14:58:52Z

← Older revision		Revision as of 14:58, 27 December 2025
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	* Notification functionality via DMA into driver memory for GPU to driver communication		* Notification functionality via DMA into driver memory for GPU to driver communication
	* 1 to 4 MB of video memory, which can either be DRAM or VRAM		* 1 to 4 MB of video memory, which can either be DRAM or VRAM
	* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU		* External RAMDAC (<code>NVDAC</code>), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU
	* Partially emulated VGA compatibility implemented via a separate PCI ID		* Partially emulated VGA compatibility implemented via a separate PCI ID
	* Multiple clock sources (<code>VPLL` for pixel clock, varying based on resolution and color depth for controlling the CRT, and `MPLL` for everything else - the card ran at 100Mhz on average)		* Multiple clock sources (<code>VPLL</code> for pixel clock, varying based on resolution and color depth for controlling the CRT, and <code>MPLL</code> for everything else - the card ran at 100Mhz on average)

	This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card:		This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card:
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	=== NV4 (RIVA TNT) ===		=== NV4 (RIVA TNT) ===


	* Hardware-accelerated stencil buffering		* Hardware-accelerated stencil buffering

Starfrost at 14:56, 27 December 2025

2025-12-27T14:56:34Z

← Older revision		Revision as of 14:56, 27 December 2025
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	* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU		* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU
	* Partially emulated VGA compatibility implemented via a separate PCI ID		* Partially emulated VGA compatibility implemented via a separate PCI ID
			* Multiple clock sources (<code>VPLL` for pixel clock, varying based on resolution and color depth for controlling the CRT, and `MPLL` for everything else - the card ran at 100Mhz on average)

	This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card:		This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card:
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	* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)		* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)
	* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit		* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit
	* The ability to scale and stretch images while receiving them from ~~the main~~ system (`USCALED` and `USTRTCH` objects)		* The ability to scale and stretch images while receiving them from system memory (`USCALED` and `USTRTCH` objects)
	* Generic image upload objects		* Generic image upload objects
	* AGP 1X bus support		* AGP 1X bus support
	* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (~~interleaved~~ Z ~~and~~ stencil ~~buffer~~), allowing much more versatile (and annoying) screen-to-screen blit capability		* DMA object submission for 3D
	* Hardware-accelerated stencil buffering		* [[NV3 RMA\|Real-Mode Access]], replacing [[NV1 RMC]]
			* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability
	* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)		* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)
	* Hardware-accelerated Z-buffering (in a released card)		* Hardware-accelerated Z-buffering (in a released card)
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	* TV-Out support		* TV-Out support
	* RAMDAC and CRTC integrated on-die		* RAMDAC and CRTC integrated on-die
	* Multiple clock sources (`VPLL` for pixel clock, varying based on resolution and color depth for controlling the CRT, and `MPLL` for everything else - the card ran at 100Mhz on average)
	* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine		* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine
	* VGA and VESA compatibility, licensed from [[Weitek]]		* VGA and VESA compatibility, licensed from [[Weitek]]
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	* Quadratic texture mapping (QTM) support		* Quadratic texture mapping (QTM) support
	* Quad patching more generally		* Quad patching more generally
			* [[NV1 DRM\|Digital rights management]]
			* [[NV1 RMC]] (replaced with RMA)
			* Sound capability (Revision B and later)
			* Sega Saturn gamepad support
	* [[NV2]] microcode		* [[NV2]] microcode
	* VLB bus support		* VLB bus support
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	* ACPI support (indicated by the PCI device ID changing to `0x0019`)		* ACPI support (indicated by the PCI device ID changing to `0x0019`)
	* Notifiers to VRAM rather than just the main system RAM (check this)		* Notifiers to VRAM rather than just the main system RAM (check this)
	* Higher RAMDAC clock (260Mhz instead of ~~200~~)		* Higher RAMDAC clock (260Mhz instead of 205)
	* Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)		* Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)
	* AGP 2X bus support		* AGP 2X bus support

	=== NV4 (RIVA TNT) ===		=== NV4 (RIVA TNT) ===
			* Hardware-accelerated stencil buffering

	=== NV5 (RIVA TNT2) ===		=== NV5 (RIVA TNT2) ===

Starfrost at 23:34, 29 April 2025

2025-04-29T23:34:57Z

← Older revision		Revision as of 23:34, 29 April 2025
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	==Rubin architecture (still in development)==		==Rubin architecture (still in development)==
	This is Nvidia's 2026 architecture for GPUs.		This is Nvidia's 2026 architecture for GPUs.

			{{GPUs}}

Starfrost at 11:52, 28 April 2025

2025-04-28T11:52:37Z

Starfrost at 11:44, 28 April 2025

2025-04-28T11:44:46Z

← Older revision		Revision as of 11:44, 28 April 2025
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	* 1 to 4 MB of video memory, which can either be DRAM or VRAM		* 1 to 4 MB of video memory, which can either be DRAM or VRAM
	* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson, for CRT control and image generation from the data sent to the GPU		* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson, for CRT control and image generation from the data sent to the GPU
			* Monochrome hardware cursor support

	This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card.		This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card:
	* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)		* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)
	* Sega Saturn game port support (in the external DAC)		* Sega Saturn game port support (in the external DAC)
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	* Hardware fog support with 24-bit colour		* Hardware fog support with 24-bit colour
	* Hardware-accelerated color space conversion		* Hardware-accelerated color space conversion
			* Hardware cursor now supports colour
	* YUV420 and YUV422 support		* YUV420 and YUV422 support
	* PC-98 support ("NEC mode")		* PC-98 support ("NEC mode")
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	* ACPI support (indicated by the PCI device ID changing to `0x0019`)		* ACPI support (indicated by the PCI device ID changing to `0x0019`)
	* Notifiers to VRAM rather than just the main system RAM (check this)		* Notifiers to VRAM rather than just the main system RAM (check this)
	* Much higher colour depths in 2D due to (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)		* Higher RAMDAC clock (260Mhz instead of 200)
			* Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)
	* AGP 2X bus support		* AGP 2X bus support

← Older revision		Revision as of 11:52, 28 April 2025
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	====Features====		====Features====
	* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw		* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw
	* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support		* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support
	* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support		* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support
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	* Notification functionality via DMA into driver memory for GPU to driver communication		* Notification functionality via DMA into driver memory for GPU to driver communication
	* 1 to 4 MB of video memory, which can either be DRAM or VRAM		* 1 to 4 MB of video memory, which can either be DRAM or VRAM
	* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson, for CRT control and image generation from the data sent to the GPU		* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU
	* ~~Monochrome hardware cursor support~~		* Partially emulated VGA compatibility implemented via a separate PCI ID

	This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card:		This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card:
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	====New features====		====New features====
	* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)		* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)
	* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the native quad patching)		* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)
	* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)		* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)
	* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit		* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit
	* The ability to scale and stretch images while receiving them from the main system (`USCALED` and `USTRTCH` objects(		* The ability to scale and stretch images while receiving them from the main system (`USCALED` and `USTRTCH` objects)
	* Generic image upload objects		* Generic image upload objects
	* AGP 1X bus support		* AGP 1X bus support
	* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the ~~3rd~~ buffer is hardcoded in the drivers to be used as a "zeta buffer" (interleaved Z and stencil buffer), allowing much more versatile (and annoying) screen-to-screen blit capability		* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (interleaved Z and stencil buffer), allowing much more versatile (and annoying) screen-to-screen blit capability
	* Hardware-accelerated stencil buffering		* Hardware-accelerated stencil buffering
	* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)		* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)
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	* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded		* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded
	* Hardware-accelerated culling		* Hardware-accelerated culling
	* Hardware-accelerated 3D alpha buffer		* Hardware-accelerated alpha buffer (for 3D acceleration)
	* Hardware-accelerated specular highlight		* Hardware-accelerated specular highlight
	* Hardware-accelerated texture offseting (varying the origin point of a texture)		* Hardware-accelerated texture offseting (varying the origin point of a texture)
	* Hardware fog support with 24-bit colour		* Hardware fog support with 24-bit colour (vertex fog only)
	* Hardware-accelerated color space conversion		* Hardware-accelerated color space conversion
	* Hardware cursor now supports colour		* Hardware cursor now supports colour
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	* RAMDAC and CRTC integrated on-die		* RAMDAC and CRTC integrated on-die
	* Multiple clock sources (`VPLL` for pixel clock, varying based on resolution and color depth for controlling the CRT, and `MPLL` for everything else - the card ran at 100Mhz on average)		* Multiple clock sources (`VPLL` for pixel clock, varying based on resolution and color depth for controlling the CRT, and `MPLL` for everything else - the card ran at 100Mhz on average)
	* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into		* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine
			* VGA and VESA compatibility, licensed from [[Weitek]]

	====Removed features====		====Removed features====
	* Quadratic texture mapping (QTM) support		* Quadratic texture mapping (QTM) support
	* Quad patching more generally		* Quad patching more generally
			* [[NV2]] microcode
	* VLB bus support		* VLB bus support
	* 3D capability at resolutions above 960720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152864		* 3D capability at resolutions above 960720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152864