GPU Clocking - Revision history

Starfrost at 17:18, 27 March 2026

2026-03-27T17:18:22Z

← Older revision		Revision as of 17:18, 27 March 2026
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	* 0x03 - Divide by 8		* 0x03 - Divide by 8
	* 0x04 - Divide by 16		* 0x04 - Divide by 16
	\|\| Applies a post-divider to the VCLK after it is calculated. Resource Manager version 2.3 only uses ~~dividers~~ of ~~one~~ and ~~two~~.		\|\| Applies a post-divider to the VCLK after it is calculated. Resource Manager version 2.3 only uses values of 1 and 2; these are used to get a finer-grained control over the exact video clock.
	\|-		\|-
	\|}		\|}

Starfrost at 21:15, 25 March 2026

2026-03-25T21:15:46Z

← Older revision		Revision as of 21:15, 25 March 2026
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	~~Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception.~~ In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref\|a}}.		In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref\|a}}.

	=== Initial clock system (1995-2002) ===		=== Initial clock system (1995-2002) ===
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	=== PLLs on the NV1 ===		=== PLLs on the NV1 ===
	The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divider; the first register is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last the <code>PDIV</code>		The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up a set of four 8-bit registers, one for each divider; the first register in the set is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last is used to hold the <code>PDIV</code>.

	{\| class="wikitable"		{\| class="wikitable"
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	On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL. The base clock is always 12.096MHz, since this is the only one supported by the STG-1764 RAMDAC.		On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL. The base clock is always 12.096MHz, since this is the only one supported by the STG-1764 RAMDAC.

	The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU can ~~run at~~.		The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU and RAMDAC can output.

	{\| class="wikitable"		{\| class="wikitable"
	\|+ <code>SGS_DAC_CONFIG_1</code> ~~V PLL~~-related bits		\|+ <code>SGS_DAC_CONFIG_1</code> VPLL-related bits
	\|-		\|-
	! Bit(s) !! Name !! Effect		! Bit(s) !! Name !! Effect

Starfrost at 21:10, 25 March 2026

2026-03-25T21:10:10Z

← Older revision		Revision as of 21:10, 25 March 2026
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	==== Configuration ====		==== Configuration ====

	On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL.		On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL. The base clock is always 12.096MHz, since this is the only one supported by the STG-1764 RAMDAC.

	The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU can run at.		The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU can run at.

Starfrost at 21:08, 25 March 2026

2026-03-25T21:08:07Z

@@ Line 36: / Line 36: @@
 ==== Configuration ====
-On NV1, the only configuration on the STG-1764 that directly corresponds to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which are used to switch off individual PLLs (mysteriously misspelt as "PPLs"); enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 would disable VPLL.
+On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL.
 ==Notes==

Starfrost: Add PLL config 000d 2:0

2026-03-25T19:54:38Z

Add PLL config 000d 2:0

← Older revision		Revision as of 19:54, 25 March 2026
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	==== Configuration ====		==== Configuration ====

			On NV1, the only configuration on the STG-1764 that directly corresponds to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which are used to switch off individual PLLs (mysteriously misspelt as "PPLs"); enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 would disable VPLL.

	==Notes==		==Notes==

Starfrost at 17:23, 25 March 2026

2026-03-25T17:23:28Z

← Older revision		Revision as of 17:23, 25 March 2026
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	=== PLLs on the NV1 ===		=== PLLs on the NV1 ===
	The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each ~~divier~~		The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divider; the first register is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last the <code>PDIV</code>

	{\| class="wikitable"		{\| class="wikitable"
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	* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),		* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),
	\|-		\|-
	\| ~~Example~~ \|\| ~~Example~~ \|\| \|\| ~~Example~~		\| <code>APLL</code> \|\| Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip \|\| DAC space <code>0x14-0x17</code> \|\| Unknown
	\|-		\|-
	\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~ \|\| ~~Example~~		\| <code>VPLL</code> \|\| Used to drive the video signal \|\| DAC space <code>0x10-0x13</code> \|\| Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.
	\|}		\|}

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	{{note\|a\|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br>		{{note\|a\|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br>
	{{note\|b\|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.		{{note\|b\|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.
	{{note\|c\|}} Only 19 bits are actually used		{{note\|c\|}} Only 19 bits are actually used by these registers (except in NV1)

Starfrost at 17:15, 25 March 2026

2026-03-25T17:15:59Z

@@ Line 16: / Line 16: @@
 === PLLs on the NV1 ===
-The NV1 has three PLLs.
+The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divier
 ==== Configuration ====

Starfrost at 17:06, 25 March 2026

2026-03-25T17:06:42Z

← Older revision		Revision as of 17:06, 25 March 2026
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	=== Initial clock system (1995-2002) ===		=== Initial clock system (1995-2002) ===

	The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at MMIO address ~~ranges~~ between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers ~~staring~~ at <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref\|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref\|b}}, with the low 8 bits making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be ~~hardcoded by~~ simply ~~taking~~ the signal coming directly from the on-board clock crystal, or configured via straps - in order to create the final clock speed using the following formula:		The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref\|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref\|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:

	<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre>		<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre>

			For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:

			<pre>(10000000 * 90) / (10 << 1)</pre>

			which resolves to exactly 45,000,000 Hz (or 45 MHz).

			Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section.

	=== PLLs on the NV1 ===		=== PLLs on the NV1 ===

Starfrost at 17:02, 25 March 2026

2026-03-25T17:02:21Z

@@ Line 1: / Line 1: @@
-Any electronic device needs a clock source to operate, and Nvidia GPUs are no exception. In early nVIDIA GPU's, the system of generating phase-locked loops (PLL) was a derivative that used by the SGS-Thomson STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}},
+Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}.
 ==Notes==
-{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.
+{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br>

Starfrost: Created page with "Any electronic device needs a clock source to operate, and Nvidia GPUs are no exception. In early nVIDIA GPU's, the system of generating phase-locked loops (PLL) was a derivative that used by the SGS-Thomson STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from NV1 until NV20. A partial break from this system was introduced with the implementation of mult..."

2026-03-25T14:47:27Z

Created page with "Any electronic device needs a clock source to operate, and Nvidia GPUs are no exception. In early nVIDIA GPU's, the system of generating phase-locked loops (PLL) was a derivative that used by the SGS-Thomson STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from NV1 until NV20. A partial break from this system was introduced with the implementation of mult..."

New page

Any electronic device needs a clock source to operate, and Nvidia GPUs are no exception. In early nVIDIA GPU's, the system of generating phase-locked loops (PLL) was a derivative that used by the SGS-Thomson STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}},

==Notes==

{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.