https://nvwiki.org/api.php?action=feedcontributions&feedformat=atom&user=StarfrostNvWiki - User contributions [en-gb]2026-05-13T14:38:07ZUser contributionsMediaWiki 1.43.1https://nvwiki.org/index.php?title=GPU_Clocking&diff=1736GPU Clocking2026-03-27T17:18:22Z<p>Starfrost: </p>
<hr />
<div>In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up a set of four 8-bit registers, one for each divider; the first register in the set is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last is used to hold the <code>PDIV</code>.<br />
<br />
{| class="wikitable"<br />
|+ Clock sources on the NV1<br />
|-<br />
! PLL !! Purpose !! MMIO address !! Notes<br />
|-<br />
| <code>MPLL</code> || The name means '''M'''emory PLL, but actually clocks both the GPU core and the Video RAM || DAC space <code>0x18-0x1C</code> ||<br />
Set by [[VBIOS]] scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: <br><br />
<br />
* '''Video BIOS''': <code>NDIV</code>=91, <code>MDIV</code>=11, <code>PDIV</code>=1 (50.033454 MHz),<br />
* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),<br />
|-<br />
| <code>APLL</code> || Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip || DAC space <code>0x14-0x17</code> || Unknown<br />
|-<br />
| <code>VPLL</code> || Used to drive the video signal || DAC space <code>0x10-0x13</code> || Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.<br />
|}<br />
<br />
==== Configuration ====<br />
<br />
On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL. The base clock is always 12.096MHz, since this is the only one supported by the STG-1764 RAMDAC.<br />
<br />
The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU and RAMDAC can output. <br />
<br />
{| class="wikitable"<br />
|+ <code>SGS_DAC_CONFIG_1</code> VPLL-related bits<br />
|-<br />
! Bit(s) !! Name !! Effect<br />
|-<br />
| 4 || Direction: '''off''' - output, '''on''' - input. || Not sure what this means. I don't know what reversing the "direction" of the VPLL would do.<br />
|-<br />
| 3 || Impedance: '''off''' - "low", '''on''' - "high" || No exact ohmage is provided. Possibly intended for board<br />
|-<br />
| 2:0 || Video clock display ||<br />
* 0x00 - Divide by 1 (don't do anything)<br />
* 0x01 - Divide by 2<br />
* 0x02 - Divide by 4<br />
* 0x03 - Divide by 8<br />
* 0x04 - Divide by 16<br />
|| Applies a post-divider to the VCLK after it is calculated. Resource Manager version 2.3 only uses values of 1 and 2; these are used to get a finer-grained control over the exact video clock. <br />
|-<br />
|}<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used by these registers (except in NV1)</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1735GPU Clocking2026-03-25T21:15:46Z<p>Starfrost: </p>
<hr />
<div>In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up a set of four 8-bit registers, one for each divider; the first register in the set is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last is used to hold the <code>PDIV</code>.<br />
<br />
{| class="wikitable"<br />
|+ Clock sources on the NV1<br />
|-<br />
! PLL !! Purpose !! MMIO address !! Notes<br />
|-<br />
| <code>MPLL</code> || The name means '''M'''emory PLL, but actually clocks both the GPU core and the Video RAM || DAC space <code>0x18-0x1C</code> ||<br />
Set by [[VBIOS]] scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: <br><br />
<br />
* '''Video BIOS''': <code>NDIV</code>=91, <code>MDIV</code>=11, <code>PDIV</code>=1 (50.033454 MHz),<br />
* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),<br />
|-<br />
| <code>APLL</code> || Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip || DAC space <code>0x14-0x17</code> || Unknown<br />
|-<br />
| <code>VPLL</code> || Used to drive the video signal || DAC space <code>0x10-0x13</code> || Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.<br />
|}<br />
<br />
==== Configuration ====<br />
<br />
On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL. The base clock is always 12.096MHz, since this is the only one supported by the STG-1764 RAMDAC.<br />
<br />
The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU and RAMDAC can output. <br />
<br />
{| class="wikitable"<br />
|+ <code>SGS_DAC_CONFIG_1</code> VPLL-related bits<br />
|-<br />
! Bit(s) !! Name !! Effect<br />
|-<br />
| 4 || Direction: '''off''' - output, '''on''' - input. || Not sure what this means. I don't know what reversing the "direction" of the VPLL would do.<br />
|-<br />
| 3 || Impedance: '''off''' - "low", '''on''' - "high" || No exact ohmage is provided. Possibly intended for board<br />
|-<br />
| 2:0 || Video clock display ||<br />
* 0x00 - Divide by 1 (don't do anything)<br />
* 0x01 - Divide by 2<br />
* 0x02 - Divide by 4<br />
* 0x03 - Divide by 8<br />
* 0x04 - Divide by 16<br />
|| Applies a post-divider to the VCLK after it is calculated. Resource Manager version 2.3 only uses dividers of one and two. <br />
|-<br />
|}<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used by these registers (except in NV1)</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1734GPU Clocking2026-03-25T21:10:10Z<p>Starfrost: </p>
<hr />
<div>Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divider; the first register is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last the <code>PDIV</code><br />
<br />
{| class="wikitable"<br />
|+ Clock sources on the NV1<br />
|-<br />
! PLL !! Purpose !! MMIO address !! Notes<br />
|-<br />
| <code>MPLL</code> || The name means '''M'''emory PLL, but actually clocks both the GPU core and the Video RAM || DAC space <code>0x18-0x1C</code> ||<br />
Set by [[VBIOS]] scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: <br><br />
<br />
* '''Video BIOS''': <code>NDIV</code>=91, <code>MDIV</code>=11, <code>PDIV</code>=1 (50.033454 MHz),<br />
* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),<br />
|-<br />
| <code>APLL</code> || Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip || DAC space <code>0x14-0x17</code> || Unknown<br />
|-<br />
| <code>VPLL</code> || Used to drive the video signal || DAC space <code>0x10-0x13</code> || Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.<br />
|}<br />
<br />
==== Configuration ====<br />
<br />
On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL. The base clock is always 12.096MHz, since this is the only one supported by the STG-1764 RAMDAC.<br />
<br />
The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU can run at. <br />
<br />
{| class="wikitable"<br />
|+ <code>SGS_DAC_CONFIG_1</code> V PLL-related bits<br />
|-<br />
! Bit(s) !! Name !! Effect<br />
|-<br />
| 4 || Direction: '''off''' - output, '''on''' - input. || Not sure what this means. I don't know what reversing the "direction" of the VPLL would do.<br />
|-<br />
| 3 || Impedance: '''off''' - "low", '''on''' - "high" || No exact ohmage is provided. Possibly intended for board<br />
|-<br />
| 2:0 || Video clock display ||<br />
* 0x00 - Divide by 1 (don't do anything)<br />
* 0x01 - Divide by 2<br />
* 0x02 - Divide by 4<br />
* 0x03 - Divide by 8<br />
* 0x04 - Divide by 16<br />
|| Applies a post-divider to the VCLK after it is calculated. Resource Manager version 2.3 only uses dividers of one and two. <br />
|-<br />
|}<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used by these registers (except in NV1)</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1733GPU Clocking2026-03-25T21:08:07Z<p>Starfrost: </p>
<hr />
<div>Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divider; the first register is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last the <code>PDIV</code><br />
<br />
{| class="wikitable"<br />
|+ Clock sources on the NV1<br />
|-<br />
! PLL !! Purpose !! MMIO address !! Notes<br />
|-<br />
| <code>MPLL</code> || The name means '''M'''emory PLL, but actually clocks both the GPU core and the Video RAM || DAC space <code>0x18-0x1C</code> ||<br />
Set by [[VBIOS]] scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: <br><br />
<br />
* '''Video BIOS''': <code>NDIV</code>=91, <code>MDIV</code>=11, <code>PDIV</code>=1 (50.033454 MHz),<br />
* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),<br />
|-<br />
| <code>APLL</code> || Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip || DAC space <code>0x14-0x17</code> || Unknown<br />
|-<br />
| <code>VPLL</code> || Used to drive the video signal || DAC space <code>0x10-0x13</code> || Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.<br />
|}<br />
<br />
==== Configuration ====<br />
<br />
On NV1, there are only two configurations on the STG-1764 that directly correspond to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which is used to switch off individual PLLs (who SGS-Thomson mysteriously misspelt as "PPLs"). The default state of these registers is off, which enables all PLLs - enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 disables VPLL.<br />
<br />
The other set of configuration which is available is contained within the lower four bits of <code>SGS_DAC_CONFIG_1</code> (SGS DAC register <code>0x0005</code>). These exclusively deal with the VPLL, since the video clock needs much more configuration due to the variety of resolutions and refresh rates that the GPU can run at. <br />
<br />
{| class="wikitable"<br />
|+ <code>SGS_DAC_CONFIG_1</code> V PLL-related bits<br />
|-<br />
! Bit(s) !! Name !! Effect<br />
|-<br />
| 4 || Direction: '''off''' - output, '''on''' - input. || Not sure what this means. I don't know what reversing the "direction" of the VPLL would do.<br />
|-<br />
| 3 || Impedance: '''off''' - "low", '''on''' - "high" || No exact ohmage is provided. Possibly intended for board<br />
|-<br />
| 2:0 || Video clock display ||<br />
* 0x00 - Divide by 1 (don't do anything)<br />
* 0x01 - Divide by 2<br />
* 0x02 - Divide by 4<br />
* 0x03 - Divide by 8<br />
* 0x04 - Divide by 16<br />
|| Applies a post-divider to the VCLK after it is calculated. Resource Manager version 2.3 only uses dividers of one and two. <br />
|-<br />
|}<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used by these registers (except in NV1)</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1732GPU Clocking2026-03-25T19:54:38Z<p>Starfrost: Add PLL config 000d 2:0</p>
<hr />
<div>Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divider; the first register is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last the <code>PDIV</code><br />
<br />
{| class="wikitable"<br />
|+ Clock sources on the NV1<br />
|-<br />
! PLL !! Purpose !! MMIO address !! Notes<br />
|-<br />
| <code>MPLL</code> || The name means '''M'''emory PLL, but actually clocks both the GPU core and the Video RAM || DAC space <code>0x18-0x1C</code> ||<br />
Set by [[VBIOS]] scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: <br><br />
<br />
* '''Video BIOS''': <code>NDIV</code>=91, <code>MDIV</code>=11, <code>PDIV</code>=1 (50.033454 MHz),<br />
* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),<br />
|-<br />
| <code>APLL</code> || Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip || DAC space <code>0x14-0x17</code> || Unknown<br />
|-<br />
| <code>VPLL</code> || Used to drive the video signal || DAC space <code>0x10-0x13</code> || Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.<br />
|}<br />
<br />
==== Configuration ====<br />
<br />
On NV1, the only configuration on the STG-1764 that directly corresponds to controlling the operation of the PLLs is the low three bits of <code>SGS_DAC_POWER_MGMT_B</code> (SGS DAC register <code>0x000D</code>), which are used to switch off individual PLLs (mysteriously misspelt as "PPLs"); enabling bit 2 will disable APLL, bit 1 will disable VPLL and bit 0 would disable VPLL.<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used by these registers (except in NV1)</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1731GPU Clocking2026-03-25T17:23:28Z<p>Starfrost: </p>
<hr />
<div>Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divider; the first register is used to hold the <code>MDIV</code>, the second the <code>NDIV</code>, the third the <code>ODIV</code> and the last the <code>PDIV</code><br />
<br />
{| class="wikitable"<br />
|+ Clock sources on the NV1<br />
|-<br />
! PLL !! Purpose !! MMIO address !! Notes<br />
|-<br />
| <code>MPLL</code> || The name means '''M'''emory PLL, but actually clocks both the GPU core and the Video RAM || DAC space <code>0x18-0x1C</code> ||<br />
Set by [[VBIOS]] scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: <br><br />
<br />
* '''Video BIOS''': <code>NDIV</code>=91, <code>MDIV</code>=11, <code>PDIV</code>=1 (50.033454 MHz),<br />
* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),<br />
|-<br />
| <code>APLL</code> || Used to drive the audio system, although I am not sure exactly what it does - perhaps it drives the AD1845 SoundPort codec chip || DAC space <code>0x14-0x17</code> || Unknown<br />
|-<br />
| <code>VPLL</code> || Used to drive the video signal || DAC space <code>0x10-0x13</code> || Clock speed dependent on chosen refresh rate and resolution. Typically within the range of 40 to a maximum of 170MHz.<br />
|}<br />
<br />
==== Configuration ====<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used by these registers (except in NV1)</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1730GPU Clocking2026-03-25T17:15:59Z<p>Starfrost: </p>
<hr />
<div>Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs which are used for different purposes and are presented in this table. In the NV1, the organisation of the registers for the clock dividers is slightly different - since they are located within the STG-1764 DAC, they are not located within MMIO but are actually located inside the internal register space of the 1764, which uses 8-bit registers. This, as well as the ultimately never used OPLL, means that each PLL takes up four 8-bit registers, one for each divier<br />
<br />
{| class="wikitable"<br />
|+ Clock sources on the NV1<br />
|-<br />
! PLL !! Purpose !! MMIO address !! Notes<br />
|-<br />
| <code>MPLL</code> || The name means '''M'''emory PLL, but actually clocks both the GPU core and the Video RAM || DAC space <code>0x18-0x1C</code> ||<br />
Set by [[VBIOS]] scripts by default, however the GPU drivers will clock the GPU themselves if the Video BIOS does not. Default values are: <br><br />
<br />
* '''Video BIOS''': <code>NDIV</code>=91, <code>MDIV</code>=11, <code>PDIV</code>=1 (50.033454 MHz),<br />
* '''Drivers''' (if PLL command cannot be found in Video BIOS): <code>NDIV</code>=100, <code>MDIV</code>=14, <code>PDIV</code>=1 (43.2 MHz),<br />
|-<br />
| Example || Example || || Example<br />
|-<br />
| Example || Example || Example || Example<br />
|}<br />
<br />
==== Configuration ====<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1729GPU Clocking2026-03-25T17:06:42Z<p>Starfrost: </p>
<hr />
<div>Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at the MMIO address range between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers starting at MMIO address <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits of the register making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be simply the clock speed of the signal coming directly from the on-board clock crystal or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
For example, if the base clock speed is 10MHz, <code>NDIV</code> is 90, <code>MDIV</code> is 10 and <code>PDIV</code> is 1, the formula resolves as:<br />
<br />
<pre>(10000000 * 90) / (10 << 1)</pre><br />
<br />
which resolves to exactly 45,000,000 Hz (or 45 MHz).<br />
<br />
Additionally, via the configuration register at <code>0x60850C</code>, various steps can be applied by the RAMDAC after this initial calculation. These settings are typically per-PLL; for example, a clock could be divided by a fixed divider, or its source can be changed. This aspect of the operation of the clock generators will be covered more in detail in the GPU-specific section. <br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs. <br />
<br />
==== Configuration ====<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1728GPU Clocking2026-03-25T17:02:21Z<p>Starfrost: </p>
<hr />
<div>Any electronic device needs a clock source to operate, and nVIDIA GPUs are no exception. In early GPUs, the system of generating phase-locked loops (PLL) was a derivative of the system used by the SGS-Thomson (now STMicro) STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}}. <br />
<br />
=== Initial clock system (1995-2002) ===<br />
<br />
The clock system in NV1 to NV2x is based in the external DAC (NV1) or on chip within in the <code>[[PRAMDAC]]</code> functional block (NV3 or later). Where it is integrated onto the chip, it is exposed in all generations at MMIO address ranges between <code>0x680300</code> and <code>0x680FFF</code>. In most cases (and in all cases prior to [[NV10]]), the registers staring at <code>0x680500</code> and ending at <code>0x6805FF</code> are used for PLL configuration; each PLL has a 32-bit{{ref|c}} register assigned to it, and there is a second 32-bit register (typically at <code>0x68050C</code>) that is used to configure these PLLs. Each PLL register is split into three dividers{{ref|b}}, with the low 8 bits making up <code>MDIV</code>, bits 15 through 8 making up <code>NDIV</code>, and a three-bit (bits 18 through 16) <code>PDIV</code>. These are combined with a base clock speed - which can be hardcoded by simply taking the signal coming directly from the on-board clock crystal, or configured via straps - in order to create the final clock speed using the following formula:<br />
<br />
<pre>(base_clock_speed * NDIV) / (MDIV << PDIV)</pre><br />
<br />
=== PLLs on the NV1 ===<br />
The NV1 has three PLLs. <br />
<br />
==== Configuration ====<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.<br><br />
{{note|b|}} The NV1 technically has a fourth divider, <code>ODIV</code>, but it is always set to a value of 1 and is effectively never used.<br />
{{note|c|}} Only 19 bits are actually used</div>Starfrosthttps://nvwiki.org/index.php?title=GPU_Clocking&diff=1727GPU Clocking2026-03-25T14:47:27Z<p>Starfrost: Created page with "Any electronic device needs a clock source to operate, and Nvidia GPUs are no exception. In early nVIDIA GPU's, the system of generating phase-locked loops (PLL) was a derivative that used by the SGS-Thomson STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from NV1 until NV20. A partial break from this system was introduced with the implementation of mult..."</p>
<hr />
<div>Any electronic device needs a clock source to operate, and Nvidia GPUs are no exception. In early nVIDIA GPU's, the system of generating phase-locked loops (PLL) was a derivative that used by the SGS-Thomson STG-1764 "Van Gogh", which was used as the external RAMDAC on the NV1. Although which PLLs existed changed, the overall system implementation was very similar from [[NV1]] until [[NV20]]. A partial break from this system was introduced with the implementation of multi-stage clocks in [[NV30]] and a full break was achieved with [[NV40]]'s implementation of clock domains{{ref|a}},<br />
<br />
==Notes==<br />
<br />
{{note|a|}} Used to allow different parts of the GPU core to run at different clock frequencies.</div>Starfrosthttps://nvwiki.org/index.php?title=NV1_known_models&diff=1726NV1 known models2026-03-19T23:07:11Z<p>Starfrost: </p>
<hr />
<div>This is a list of known card models of the NVidia NV1. Attempts have been made to sort the companies by number of units sold.<br />
<br />
=== Diamond Multimedia ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| Edge 3D 2120 || DRAM || 1 MB || STG2000X<br />
|-<br />
| Edge 3D 2200 || DRAM || 2 MB || STG2000X (usually)<br />
|-<br />
| Edge 3D 3240 || VRAM || 2 MB || NV1<br />
|-<br />
| Edge 3D 3400 || VRAM || 4 MB (2MB on "3D Memory Module") || NV1<br />
|}<br />
<br />
=== Videoforte ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| VF64-3DG-01 || DRAM || 2 MB || NV1<br />
|-<br />
| VF64-3DG-02 || DRAM || 4 MB || NV1<br />
|-<br />
| MAG Japan MultimediaCard MAG-8000 || EDO DRAM || 4 MB || NV1 (Seems to be a rebranded version of the 3DG-02, since the driver CD has a "VF64-3DG" folder. Serial number on listing was 000081, so very few were ever produced)<br />
|}<br />
<br />
=== Jazz Multimedia ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| 3D Magic || DRAM || 2 MB || NV1<br />
|-<br />
| 3D Magic VRAM (cancelled) || VRAM || Unknown || Unknown<br />
|-<br />
|}<br />
<br />
<br />
=== Leadtek ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| Proview GD400 (very few produced - all 9547) || DRAM || 1 MB || STG-2000X<br />
|-<br />
| Proview GV500 (cancelled) || VRAM || 2 MB || NV1<br />
|-<br />
|}<br />
<br />
<br />
=== Unknown ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| Turbo 2000B || DRAM || 1 MB or 2 MB || NV1<br />
|-<br />
|}<br />
<br />
=== YUAN ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| JRS-3DS-100 (v3.0, v6.0, v6.9 known) || DRAM || 2 MB || STG-2000X<br />
|-<br />
|}</div>Starfrosthttps://nvwiki.org/index.php?title=NV1_known_models&diff=1725NV1 known models2026-03-19T23:06:52Z<p>Starfrost: </p>
<hr />
<div>This is a list of known card models of the NVidia NV1. Attempts have been made to sort the companies by number of units sold.<br />
<br />
=== Diamond Multimedia ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| Edge 3D 2120 || DRAM || 1 MB || STG2000X<br />
|-<br />
| Edge 3D 2200 || DRAM || 2 MB || STG2000X (usually)<br />
|-<br />
| Edge 3D 3240 || VRAM || 2 MB || NV1<br />
|-<br />
| Edge 3D 3400 || VRAM || 4 MB (2MB on "3D Memory Module") || NV1<br />
|}<br />
<br />
=== Videoforte ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| VF64-3DG-01 || DRAM || 2 MB || NV1<br />
|-<br />
| VF64-3DG-02 || DRAM || 4 MB || NV1<br />
|-<br />
| MAG Japan MultimediaCard MAG-8000 || EDO DRAM || 4 MB || NV1 (Seems to be a rebranded version of the 3DG-02, since the driver CD has a "VF64-3DG" folder)<br />
|}<br />
<br />
=== Jazz Multimedia ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| 3D Magic || DRAM || 2 MB || NV1<br />
|-<br />
| 3D Magic VRAM (cancelled) || VRAM || Unknown || Unknown<br />
|-<br />
|}<br />
<br />
<br />
=== Leadtek ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| Proview GD400 (very few produced - all 9547) || DRAM || 1 MB || STG-2000X<br />
|-<br />
| Proview GV500 (cancelled) || VRAM || 2 MB || NV1<br />
|-<br />
|}<br />
<br />
<br />
=== Unknown ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| Turbo 2000B || DRAM || 1 MB or 2 MB || NV1<br />
|-<br />
|}<br />
<br />
=== YUAN ===<br />
{| class="wikitable"<br />
|+ Model information<br />
|-<br />
! Brand name !! RAM type !! RAM amount !! Chip branding<br />
|-<br />
| JRS-3DS-100 (v3.0, v6.0, v6.9 known) || DRAM || 2 MB || STG-2000X<br />
|-<br />
|}</div>Starfrosthttps://nvwiki.org/index.php?title=NV1&diff=1724NV12026-02-03T23:55:49Z<p>Starfrost: </p>
<hr />
<div>{{Template:Infobox GPU<br />
|title='''NV1'''<br />
|architecture=NV1<br />
|branding=SGS-Thomson STG2000; NV1; OEM cards: Diamond Edge 3D; Jazz Multimedia 3D Magic<br />
|announcement_date=22 May 1995<br />
|release_date=Q3 1995<br />
|end_of_production=Likely between February 26, 1996 and March 3, 1996<br />
|pci_vendor_id=<code>104a</code> (SGS-Thomson; DRAM version); <code>10de</code> (NVidia; VRAM version)<br />
|pci_device_id=<code>0008</code> (main GPU)<br><code>0009</code> (VGA emulation layer)<br />
|buses_supported=VLB (never commercialised), PCI<br />
|directx_version=2.0 (badly software emulated)<br />
|opengl_version=Not supported<br />
}}<br />
<br />
<br />
TODO<br />
<br />
==Architecture reference==<br />
* [[NV1 RMC]]<br />
* [[NV1 known units]]<br />
* [[PTIMER]]<br />
* [[VBIOS]]<br />
<br />
==Notes==<br />
* 644 registers, plus some extra that function as arrays<br />
<br />
==See also==<br />
* [[NV1 known models]]<br />
* [[NV1 known units]]<br />
<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=Hardware_errata&diff=1723Hardware errata2026-01-19T20:09:02Z<p>Starfrost: </p>
<hr />
<div>This is a list of known hardware errata in Nvidia graphics cards<br />
<br />
== Shared across multiple GPUs ==<br />
<br />
== NV3 ==<br />
<br />
=== Early VBIOS bugs ===<br />
While not technically a hardware errata, due to an unknown issue with the video BIOS code in certain very early NVidia RIVA 128 units, certain VGA functions are broken. This causes garbage characters to appear inside of the Windows 98 Startup menu while trying to boot from CD-ROM. <br />
<br />
This bug is known to exist in very early STB Velocity 128 units with VBIOS version 1.60, dated 8 August 1997, with GPUs manufactured in July 1997; this behaviour was discovered on a chip manufactured in week 33 of 1997, VRAM manufactured week 25, a 1.60 Velocity 128 VBIOS with a label on top reading <code>9/17/97</code> and a final board manufacture date of 10 October 1997, and was later confirmed when this VBIOS was dumped and emulated. This behaviour does not appear to exist on VBIOSes dated 3 September 1997 and later, although it is currently unknown whether this behaviour exists in older VBIOS versions, with VBIOS versions as old as 1.40 being known to exist (however this VBIOS may have only been present in engineering samples). There is no workaround for this bug other than potentially updating the VBIOS, although using a method that involves mashing the down arrow key you can still get into Windows 98 Setup with no problems. <br />
<br />
It is unclear if this issue originates from Nvidia, or any modifications STB Systems may have made to the VBIOS code. While bitrot of the VBIOS flash chip was considered as a possibility, dumping the VBIOS multiple times and via multiple methods (both by reading out the <code>PROM</code> region and reading directly from the below-1 MB area reserved for the VBIOS) proved that it was fully intact.<br />
<br />
=== Extremely strange behaviour on turning off interrupts ===<br />
On a NV3T (RIVA 128 ZX) stepping A2 card, turning off interrupts did not turn off interrupts, but instead caused all areas of MMIO not to be mapped to a register to endlessly decrement, wrapping over to <code>0xFF</code> when they reached zero. The card showed no outward symptoms of this extremely strange behaviour and otherwise continued to operate normally. <br />
<br />
=== CRTC scanline counter needs to be read twice ===<br />
Under some circumstances, the CRTC scanline counter needs to be read twice to get an accurate result.<br />
<br />
=== NV3 DMA submission error ===<br />
In the following circumstances: <br />
<br />
* A 16 or 32-bit blit is occurring via the DMA method;<br />
* the source area has a width of less than 16 pixels;<br />
* the format of the blit has alpha transparency;<br />
* the blit needs to be stretched during transfer;<br />
* the source of the blit is in the GPU local VRAM;<br />
* the NV3 card is Revision A or B (i.e. an original RIVA 128 rather than a ZX).<br />
<br />
The data may be transferred incorrectly, although the mechanism of such is not known. The drivers work around this by sending the pitch of the data to be sent in bytes, rather than the width in pixels. The older hardware revisions may not account for the pitch not being the same as the width (this is further suggested by the same code not being in the 8bpp blitting code) in this case.<br />
<br />
== NV4 ==<br />
<br />
=== Random VRAM corruption at pixel clocks above 160MHz using 64-bit bus ===<br />
Due to a bug in the NV4 bus arbitration hardware to do with both memory refreshes and pagetable TLB misses, random VRAM corruption may occur if the [[PSTRAPS|straps]] are set such that the card is configured to use a 64-bit bus (used in many lower-end NV3, NV4 and NV5 configurations), and the pixel clock is above 160Mhz. This, in practice, requires a refresh rate of above 60Hz, a framebuffer configured to use 32 bits per pixel mode (which 24 bits per pixel is internally considered to be as well), and a resolution of 1600x1200 or higher. Nvidia worked around this in their drivers by simply preventing the selection of any video mode where the resolution is 1600x1200x32 and the refresh rate is above 60Hz.<br />
<br />
=== [[VBIOS]] mapped to wrong location ===<br />
Official documentation for NV4-based products states that the VBIOS should be mapped to <code>0x300000-0x300FFF</code> (<code>PROM</code>) in BAR0. However, in practice, according to dumps on multiple revision A5 NV4 chips, it is actually mapped to <code>0x700000-0x70FFFF</code>, which clashes with the first <code>0xFFFF</code> bytes of [[NV4 PRAMIN|PRAMIN]] and makes that range of RAMIN unusavble (unless the ROM is disabled using PCI configuration space register 0x31?); the area that NVIDIA seemingly intended the Video BIOS to be mapepd to instead simply returns <code>0xFF</code> for all bytes. However, this is not a problem in practice since only the areas of RAMIN starting at an offset <code>0x10000</code> are actually used by Nvidia's drivers due to where the location of [[NV4 RAMHT|RAMHT]] is initialised to. However, it is of concern to emulator developers and those individuals hoping to program the GPU registers directly.<br />
<br />
=== <code>PCRTC_CONFIG</code> cannot be accessed unless another CRTC register is accessed first ===<br />
The NV4 CRTC config register (configuring the [[Weitek]] licensed CRTC) cannot be accessed (for read or write) unless another CRTC register is read first on NV4 revision A. This was fixed in revision B of the NV4.<br />
<br />
=== TV mode: Cursor & overlay position inaccuracies ===<br />
The cursor, as well as the overlay position may have a slightly inaccurate position if an NV4-based card is connected to a TV and the straps are configured for TV Mode. This is worked around in the drivers by Nvidia by adding an adjust value - <code>0x00010400</code> in the case of the overlay position and <code>0x00010004</code> for the window start position.</div>Starfrosthttps://nvwiki.org/index.php?title=Hardware_errata&diff=1722Hardware errata2026-01-19T20:08:38Z<p>Starfrost: </p>
<hr />
<div>This is a list of known hardware errata in Nvidia graphics cards<br />
<br />
== Shared across multiple GPUs ==<br />
<br />
== NV3 ==<br />
<br />
=== Early VBIOS bugs ===<br />
While not technically a hardware errata, due to an unknown issue with the video BIOS code in certain very early NVidia RIVA 128 units, certain VGA functions are broken. This causes garbage characters to appear inside of the Windows 98 Startup menu while trying to boot from CD-ROM. <br />
<br />
This bug is known to exist in very early STB Velocity 128 units with VBIOS version 1.60, dated 8 August 1997, with GPUs manufactured in July 1997; this behaviour was discovered on a chip manufactured in week 33 of 1997, VRAM manufactured week 25, a 1.60 Velocity 128 VBIOS with a label on top reading <code>9/17/97</code> and a final board manufacture date of 10 October 1997, and was later confirmed when this VBIOS was dumped and emulated. This behaviour does not appear to exist on VBIOSes dated 3 September 1997 and later, although it is currently unknown whether this behaviour exists in older VBIOS versions, with VBIOS versions as old as 1.40 being known to exist (however this VBIOS may have only been present in engineering samples). There is no workaround for this bug other than potentially updating the VBIOS, although using a method that involves mashing the down arrow key you can still get into Windows 98 Setup with no problems. <br />
<br />
It is unclear if this issue originates from Nvidia, or any modifications STB Systems may have made to the VBIOS code. While bitrot of the VBIOS flash chip was considered as a possibility, dumping the VBIOS multiple times and via multiple methods (both by reading out the <code>PROM</code> region and reading directly from the below-1 MB area reserved for the VBIOS) proved that it was fully intact.<br />
<br />
=== Extremely strange behaviour on turning off interrupts ===<br />
On a NV3T (RIVA 128 ZX) stepping A2 card, turning off interrupts did not turn off interrupts, but instead caused all areas of MMIO not to be mapped to a register to endlessly decrement, wrapping over to <code>0xFF</code> when they reached zero. The card showed no outward symptoms of this extremely strange behaviour and otherwise continued to operate normally. <br />
<br />
=== CRTC scanline counter needs to be read twice ===<br />
Under some circumstances, the CRTC scanline counter needs to be read twice to get an accurate result.<br />
<br />
=== NV3 DMA submission error ===<br />
In the following circumstances: <br />
<br />
* A 16 or 32-bit blit is occurring via the DMA method;<br />
* the source area has a width of less than 16 pixels;<br />
* the format of the blit has alpha transparency;<br />
* the blit needs to be stretched during transfer;<br />
* the source of the blit is in the GPU local VRAM;<br />
* the NV3 card is Revision A or B (i.e. an original RIVA 128 rather than a ZX).<br />
<br />
The data may be transferred incorrectly, although the mechanism of such is not known. The drivers work around this by sending the pitch of the data to be sent in bytes, rather than the width in pixels. The older hardware revisions may not account for the pitch not being the same as the width (this is further suggested by the same code not being in the 8bpp blitting code) in this case.<br />
<br />
== NV4 ==<br />
<br />
=== Random VRAM corruption at pixel clocks above 160MHz using 64-bit bus ===<br />
Due to a bug in the NV4 bus arbitration hardware to do with both memory refreshes and pagetable TLB misses, random VRAM corruption may occur if the [[PSTRAPS|straps]] are set such that the card is configured to use a 64-bit bus (used in many lower-end NV3, NV4 and NV5 configurations), and the pixel clock is above 160Mhz. This, in practice, requires a refresh rate of above 60Hz, a framebuffer configured to use 32 bits per pixel mode (which 24 bits per pixel is internally considered to be as well), and a resolution of 1600x1200 or higher. Nvidia worked around this in their drivers by simply preventing the selection of any video mode where the resolution is 1600x1200x32 and the refresh rate is above 60Hz.<br />
<br />
=== [[VBIOS]] mapped to wrong location ===<br />
Official documentation for NV4-based products states that the VBIOS should be mapped to <code>0x300000-0x300FFF</code> (<code>PROM</code>) in BAR0. However, in practice, according to dumps on multiple revision A5 NV4 chips, it is actually mapped to <code>0x700000-0x70FFFF</code>, which clashes with the first <code>0xFFFF</code> bytes of [[NV4 PRAMIN|PRAMIN]] and makes that range of RAMIN unusavble (unless the ROM is disabled using PCI configuration space register 0x31?); the area that NVIDIA seemingly intended the Video BIOS to be mapepd to instead simply returns <code>0xFF</code> for all bytes. However, this is not a problem in practice since only the areas of RAMIN starting at an offset <code>0x10000</code> are actually used by Nvidia's drivers due to where the location of [[NV4 RAMHT|RAMHT]] is initialised to. However, it is of concern to emulator developers and those individuals hoping to program the GPU registers directly.<br />
<br />
=== <code>PCRTC_CONFIG</code> cannot be accessed unless another CRTC register is accessed first ===<br />
The NV4 CRTC config register (configuring the [[Weitek]] licensed CRTC) cannot be accessed (for read or write) unless another CRTC is read first on NV4 revision A. This was fixed in revision B of the NV4.<br />
<br />
=== TV mode: Cursor & overlay position inaccuracies ===<br />
The cursor, as well as the overlay position may have a slightly inaccurate position if an NV4-based card is connected to a TV and the straps are configured for TV Mode. This is worked around in the drivers by Nvidia by adding an adjust value - <code>0x00010400</code> in the case of the overlay position and <code>0x00010004</code> for the window start position.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1721NVPlay2026-01-13T16:57:19Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| released = {{Start date and age|2025|04|14|df=y}}<br />
| latest release version = 1.0.1<br />
| latest release date = {{Start date and age|2026|01|05|df=y}}<br />
| latest preview version = 2.0.0.103; 1.1.0.102<br />
| latest preview date = {{Start date and age|2026|01|13|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]], [[wikipedia:Diagnostic program|Diagnostic program]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1720NVPlay2026-01-05T19:44:45Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| released = {{Start date and age|2025|04|14|df=y}}<br />
| latest release version = 1.0.1<br />
| latest release date = {{Start date and age|2026|01|05|df=y}}<br />
| latest preview version = 2.0.0.75<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]], [[wikipedia:Diagnostic program|Diagnostic program]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1719NVPlay2026-01-05T02:15:48Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| released = {{Start date and age|2025|04|14|df=y}}<br />
| latest release version = 1.0.0<br />
| latest release date = {{Start date and age|2025|12|31|df=y}}<br />
| latest preview version = 2.0.0.59<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]], [[wikipedia:Diagnostic program|Diagnostic program]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1718NVPlay2026-01-05T02:13:15Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| released = {{Start date and age|2025|04|14|df=y}}<br />
| latest release version = 1.0.0<br />
| latest release date = {{Start date and age|2025|12|31|df=y}}<br />
| latest preview version = 2.0.0.59<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1717NVPlay2026-01-05T02:13:05Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| released = {{Start date and age|2025|04|14}}<br />
| latest release version = 1.0.0<br />
| latest release date = {{Start date and age|2025|12|31|df=y}}<br />
| latest preview version = 2.0.0.59<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1716NVPlay2026-01-05T02:12:51Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| released = {{Start date and age|2024|04|14}}<br />
| latest release version = 1.0.0<br />
| latest release date = {{Start date and age|2025|12|31|df=y}}<br />
| latest preview version = 2.0.0.59<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1715NVPlay2026-01-05T02:12:12Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| released = {{Start date and age|2024|04|25}}<br />
| latest release version = 1.0.0<br />
| latest release date = {{Start date and age|2025|12|31|df=y}}<br />
| latest preview version = 2.0.0.59<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1714NVPlay2026-01-05T02:11:40Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| latest release version = 1.0.0<br />
| latest release date = {{Start date and age|2025|12|31|df=y}}<br />
| latest preview version = 2.0.0.59<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1713NVPlay2026-01-05T02:11:20Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| latest release = 1.0.0<br />
| latest release date = {{Start date and age|2025|12|31|df=y}}<br />
| latest preview version = 2.0.0.59<br />
| latest preview date = {{Start date and age|2026|01|05|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=List_of_GPUs&diff=1712List of GPUs2025-12-31T01:54:20Z<p>Starfrost: </p>
<hr />
<div>This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) often produced dozens of SKUs for a particular "series" and the list would be full of hundreds of almost identical graphics cards.<br />
<br />
==Quadratic texture mappers==<br />
<br />
=== NV0 ===<br />
{{Main|NV0}}<br />
Not actually a GPU, but a series of VxD drivers under Windows 3.x to emulate the NV1 environment before it was ready. <br />
<br />
==== Features ====<br />
* Unknown<br />
<br />
=== NV1 ===<br />
{{Main|NV1}}<br />
<br />
The first GPU (or as it was dubbed by Nvidia at the time, "Multimedia Accelerator") designed by Nvidia and manufactured by SGS-Thomson Microelectronics (now STMicroelectronics), designed starting in 1993 and ending with its release in 1995. Its name is a contraction of "GX Next Version" (GXNV), as the GPU was designed by the same person, Curtis Priem, who designed the Sun GX for graphics workstations; Huang mandated the rename to NV1 for legal reasons. Unlike all later released Nvidia graphics cards, it does not render using triangles as the fundamental basis of graphical rendering but instead by using quad patching to implement quadratic texture mapped (QTM)'d curves. This has advantages for certain applications, such as computer-aided design and smooth curved surfaces, but is much more cumbersome for programming and game engine development, which was the intended market. There are also many other unique features, as Nvidia's strategy at this time was to attempt to monopolise all of the I/O on the graphical hardware. Ultimately it failed, due to its high cost, poor VGA functionality, and poor Direct3D (which was based on graphical hardware), and was discontinued in Q1 of 1996, not long after its launch. Apparently, at least 250,000 chips were sold, but most of them were returned without ever being put into cards due to poor sales; the poor sales also appear to have led to the cancellation of a 350 nm die shrink<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/090904.pdf (Microprocessor Report, July 10, 1995)</ref>.<br />
<br />
The original text (barring some minor redactions) of the "Strategic Collaboration Agreement" to develop the Nvidia NV1, RIVA 128 (NV3) and RIVA 128 ZX (NV3T) with SGS-Thomson can be found in a 1998 SEC filing, as it was an agreement that materially affected investors scoping out the company for potential investment during the IPO process<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref>.<br />
<br />
====Features====<br />
* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw<br />
* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support<br />
* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support<br />
* 3D Quadrilateral and Triangle rendering (however much slower than QTMs and not the primary focus)<br />
* Two-cache Gray-code indexed FIFO, [[PFIFO]] (one, <code>CACHE0</code>, with a size of one; another with 32 total entries) for graphical command ("object" submission)<br />
* Pseudo-C++ object system for total lunacy in design<br />
* Multi-channel DMA engine with 8 DMA channels, each with 8 subchannels (selectable by "context switching"), which can also be written to via PIO (<code>NV_USER</code>)<br />
* Oddly addressed [[RAMIN]] area for object submission<br />
* Hash table ([[RAMHT]]) for further object caching<br />
* Built-in error handling for invalid object submission via sending to [[RAMRO]]<br />
* Notification functionality via DMA into driver memory for GPU to driver communication<br />
* 1 to 4 MB of video memory, which can either be DRAM or VRAM<br />
* External RAMDAC (<code>NVDAC</code>), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU<br />
* Partially emulated VGA compatibility implemented via a separate PCI ID<br />
* Multiple clock sources (<code>VPLL</code> for pixel clock, varying based on resolution and color depth for controlling the CRT, and <code>MPLL</code> for everything else - the card ran at 100Mhz on average)<br />
<br />
This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card: <br />
* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)<br />
* Sega Saturn game port support (in the external DAC)<br />
* Partial VGA compatibility, largely emulated in software<br />
* EEPROM for storage of chip ID<br />
* [[NV1/DRM|Unused hardware-implemented encryption and digital rights management functionality]]<br />
* VESA Local Bus support, as well as PCI (seemingly only PCI versions were released as VLB was relatively short-lived)<br />
* Proprietary NVLIB API to avoid direct hardware programming <br />
<br />
=== NV2 ===<br />
{{Main|NV2}}<br />
The NV2 was a GPU designed under contract from Sega for the "Saturn V08", the first version of the project that became the Sega Dreamcast, starting in May 1995<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref> around the time of the announcement of the NV1. It was cancelled, at some point around early to mid 1996, due to internal pressure from Sega (especially their AM2 division) to move to a triangle-based model, combined with possible intransigence on Nvidia's part. SEGA still paid (loaned then forgave) NVIDIA 5 million dollars, which prevented the company from going bankrupt immediately. Most information on the technical implementation of the NV2 comes from Don Goddard, who was the main employee tasked with programming the NV2 (via a software emulator on the NV1) - which he described as "hella confusing", and with no debugging - at Sega of America.<br />
<br />
====New features====<br />
* Proto-shader microcode similar to the Nintendo 64 Reality Coprocessor & Reality Signal Processor GPU to handle texture compression, lighting, positions, and texture U/V coordinates<br />
* Possibly hardware-accelerated lighting <br />
* Color compression<br />
* Hardware-accelerated Z-buffering<br />
* Cartridge DMA (yes, cartridge) via the <code>PCART</code> subsystem<br />
* No VGA compatibility, as it was a game console GPU<br />
<br />
The status on if the NV2 ever worked as physical hardware is disputed; it was certainly taped out (even if only for one stepping, A0), and failed a demonstration to Sega, which may have triggered the cancellation of the project. However, some sources claim that a single engineer, Wayne Kogachi<ref>''The Nvidia Way'', Tae Kim, page 62</ref>, was assigned to and was successfully able to product a working chip. This was done in order to trigger an $1 million milestone payment, which was required due to the company's zero sales at the time. <br />
<br />
=== NV3 (Quadratic Texture Mapped version) ===<br />
{{Main|NV3 (QTM)}}<br />
<br />
Before [[David Kirk]] was hired at Nvidia, Nvidia were planning to launch a QTM-based "NV3" (entirely separate to the product launched as the Riva 128), a 100% functional superset of NV1 for PCs. It was announced around March 1996<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/100304.pdf (Microprocessor Report, March 5, 1996)</ref> for volume production in October of 1996, and was apparently going to be used in a home theater system by Lexicon, as the audio chip, provide an integrated RAMDAC and be generally much faster. It was most likely cancelled extremely quickly after its announcement, owing to Nvidia's new direction of developing triangle-based graphics accelerators. Very little else is known about it (other than the fact it would apparently be able to process 500,000 50-pixel triangles per second) and the original press release, published on 22 January 1996, does not mention the NV3, but also calls the NV1 NVIDIA's "first generation" product<ref>https://web.archive.org/web/19961112163232/http://www.nvidia.com/corporate/prlexicon.html ("LEXICON AND NVIDIA TEAM UP FOR NEXT GENERATION OF PC ENTERTAINMENT SOUND"; NVIDIA Corporation; 22 January 1996)</ref>. However, it does not seem to be a typo on the part of Microprocessor Report since it is repeated many times and explicitly stated to be a PC graphics card, which the NV2 was not.<br />
<br />
==Fixed function, no T&L (RIVA)==<br />
<br />
=== NV3 (RIVA 128)===<br />
{{Main|NV3}}<br />
[[David Kirk]] left Crystal Dynamics to replace [[Curtis Priem]] as the manager of GPU development at Nvidia after the NV2 was cancelled, and decided that sane design was the best way to go. Across nine months in 1996 and 1997, a triangle-based design was thrown together (completed in approximately January 1997?), tested extensively on a hardware simulator from another nearly-bankrupt company called [[Ikos]] (as Nvidia did not have the money for more than one revision of the chip without sales), and then taped out around 1 April 1997<ref>https://www.wave-report.com/1997%20Wave%20issues/wave707.html#707.4 (WAVE Report, 14 April 1997, "2 weeks out of fab")</ref>. The card was demoed at CGDC 1997, with Direct3D drivers that had only had crash bugs fixed hours before the demo and OpenGL drivers that had only achieved any functionality at all two days earlier<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/qAKzlj9qf5Q/m/lBQ25B1dhJMJ (USENET; "3D Chips at CGDC", Samuel S. Paik, 28 April 1997)</ref>, and were apparently "slow and buggy". The card launched as the "RIVA 128" ('''R'''eal-time '''I'''nteractive '''V'''ideo and '''A'''nimation accelerator, '''128'''-bit bus) in August 1997 (while the earliest known drivers are GDI-only NT 4.0 drivers compiled on 17 July 1997, these seem to have simply been an accidental release of pre-release drivers with an OEM card as they are an extreme outlier, with the earliest Win9x drivers and generic Nvidia drivers dated mid-August). OpenGL drivers were first released in alpha form in December 1997 and full form in March 1998. <br />
<br />
The card was very successful, at least compared to previous models and caused Nvidia's revenue to jump from $5.5 million in the first nine months of 1997 to $23.5 million in the last few months - several million were manufactured. Driver support ended in early 1999 (although 2D-only drivers continued to be compiled for Windows 2000 and XP until 2001) and manufacturing ended some time in mid to late 1999 for the ZX variant.<br />
<br />
====New features====<br />
* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)<br />
* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)<br />
* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)<br />
* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit<br />
* The ability to scale and stretch images while receiving them from system memory (<code>USCALED</code> and <code>USTRTCH</code> objects)<br />
* Generic image upload objects<br />
* AGP 1X bus support<br />
* DMA object submission for 3D<br />
* [[NV3 RMA|Real-Mode Access]], replacing [[NV1 RMC]]<br />
* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability<br />
* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)<br />
* Hardware-accelerated Z-buffering (in a released card)<br />
* Perspective-correct texture mapping (QTMs used forward texture mapping)<br />
* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded<br />
* Hardware-accelerated culling<br />
* Hardware-accelerated alpha buffer (for 3D acceleration)<br />
* Hardware-accelerated specular highlight<br />
* Hardware-accelerated texture offseting (varying the origin point of a texture)<br />
* Hardware fog support with 24-bit colour (vertex fog only)<br />
* Hardware-accelerated color space conversion <br />
* Hardware cursor now supports colour<br />
* Configurable frustum culling modes (clockwise/counterclockwise)<br />
* YUV420 and YUV422 support<br />
* PC-98 support changed to "NEC mode" strap rather than different VBIOS<br />
* Moved to a new 350 nm process rather than 500 nm<br />
* "Mediaport" on-card that allows plugging in external MPEG decoder<br />
* TV-Out support<br />
* RAMDAC and CRTC integrated on-die<br />
<br />
* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine<br />
* VGA and VESA compatibility, licensed from [[Weitek]]<br />
<br />
====Removed features====<br />
* Quadratic texture mapping (QTM) support<br />
* Quad patching more generally<br />
* [[NV1 DRM|Digital rights management]]<br />
* [[NV1 RMC]] (replaced with RMA)<br />
* Sound capability (Revision B and later)<br />
* Sega Saturn gamepad support<br />
* [[NV2]] microcode<br />
* VLB bus support<br />
* 3D capability at resolutions above 960*720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152*864<br />
<br />
=== NV3T (RIVA 128 ZX) ===<br />
{{Main|NV3#NV3T}}<br />
<br />
When Intel announced the Intel i740 GPU, Nvidia got cold feet and decided to rev a new version, revision C, of the RIVA 128, add some minor features, allow for 8 MB of VRAM and rebrand it as a new version.<br />
<br />
====Added features====<br />
* 8 MB of VRAM, rather than just 2 or 4<br />
* 1080p and 1920x1200 resolution support in the BIOS<br />
* PFIFO CACHE1 is now 64 slots deep instead of 32 <br />
* 3D capability at resolutions above 960*720 is possible again<br />
* The ability to write to <code>PSTRAPS</code><br />
* ACPI support (indicated by the PCI device ID changing to <code>0x0019</code>)<br />
* Notifiers to VRAM rather than just the main system RAM (check this)<br />
* Higher RAMDAC clock (260Mhz instead of 205)<br />
** Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)<br />
* AGP 2X bus support<br />
<br />
=== NV4 (RIVA TNT) ===<br />
By April of 1997, revenues were soaring and the future of the company was secured. Therefore, nVIDIA began work on their next generation design, which would have enough time in the oven to be polished and finished on release; large refactors of both the hardware and software platforms used since [[NV1]] were undertaken. Due to this (the NV4 is the first GPU supported by modern-style multi-chip drivers, rather than requiring a separate Resource Manager branch for every single model of hardware), for a very long time (until just before the debut of CUDA) this design was considered to be the "base" level that all other designs extended, with newer GPUs being "NV4 compatible". Despite having to be underclocked quite severely, it was still almost as fast as the Voodoo2 with several serious advantages; the GPU was released as the RIVA TNT in August 1998 and, despite some controversy over its underclocking, sold and reviewed very well. <br />
<br />
====Added features====<br />
* Up to 16 MB VRAM<br />
* Hardware-accelerated stencil buffering (8-bit); can be interlaced with the Z buffer for higher performance and lower memory bandwidth use ("zeta buffer")<br />
* 16 DMA channels instead of 8<br />
* Pushbuffer-based DMA object submission<br />
** They can be 124 or 512 bytes<br />
* 32-bit 3D rendering<br />
* Dual texture pipes that can rasterise two texels per cycle<br />
* PFIFO CACHE1 is now 128 slots deep instead of 64<br />
* Class system in GPU is now the same as the class system in the Resource Manager<br />
* FIFO timeslice scheduler <br />
* [[NV4 PGRAPH#Colour combiners|Colour combiners]], two proto-shaders that operate on the fragments right before rasterisation - the result of one can be passed into the other.<br />
* Unified memory support for iGPUs<br />
* Some DVD acceleration support (such as support for various DVD colour formats like <code>A4V6YB6A4U6YA6</code>), but I am not sure if it was finished<br />
* Trilinear filtering<br />
* Anisotropic filtering (kind of crappy and approximated)<br />
* Texture swizzling<br />
* Configurable Z buffer format (IEEE 754 float or fixed point)<br />
* Up to 6 buffers<br />
** Ability to swizzle buffers 2 and 5<br />
** Buffers are now optionally part of the MMU with a base and limit<br />
* Somewhat different <code>NvNotification</code> format<br />
* Ability to scramble the framebuffer<br />
* MMIO register to change start of CRTC VGA framebuffer<br />
* Even more debug registers, including ping-pong mode (what??)<br />
* An extremely basic two instruction set DMA bytecode to allow jumping between different parts of DMA streams<br />
* 16bpp modes are now actually 16bpp by default, not 15bpp<br />
* Buffer formats <code>Z8R8G8B8</code>, <code>O1Z7R8G8B8</code> and <code>O1A7R8G8B8</code> for interlacing Z and colour buffers<br />
* YUV buffer formats <code>V8YB8U8YA8</code> and <code>YB8V8YA8U8</code> <br />
* <code>FFINTFC</code> registers for internal state information <br />
* [[Weitek]] CRTC extended sequencer register locking was moved from sequencer register 0x6 to CRTC register 0x1F<br />
** CRTC extended sequencer registers can be unlocked for read or both read and write. In NV3 they can only be unlocked for read and write<br />
* <code>PRAMDAC</code> can output 24 bit colour - the GPU still only works with 8, 16 and 32 bit colour, and it doesn't seem these modes are exposed to the display drivers.<br />
<br />
====Removed features====<br />
* 1 MB VRAM (2 and 4 are actually supported but none were ever made, although 4 MB was announced)<br />
* <code>U*</code> registers. Instead, method information can be obtained via determining which Resource Manager methods are sent to hardware.<br />
* [[NV3 DMA]] mode submission<br />
* PC-98 support<br />
* Microsoft zero-order hold texture (<code>ZOH_MS</code>) coordinate interpolation <br />
* <code>PRAMDAC_GENERAL_CONTROL_565_MODE</code> is removed, replaced with the <code>ALT_MODE</code> bit, which can cause 16bpp to become 15bpp and 32bpp to become 24bpp<br />
<br />
=== NV5 (RIVA TNT2) ===<br />
<br />
==== NV5ULTRA (RIVA TNT2 Ultra) ====<br />
==== NV5VANTA (RIVA TNT2 Vanta; Vanta LT) ====<br />
==== NV6 (RIVA TNT2 M64) ====<br />
<br />
<br />
==Celsius architecture: Fixed function, T&L==<br />
<br />
==Kelvin architecture: Programmable shaders==<br />
<br />
==Rankine architecture==<br />
<br />
==Curie architecture==<br />
<br />
==Tesla architecture: GPGPU, unified shaders and CUDA ==<br />
<br />
==Tesla 2.0 architecture (GT2xx)==<br />
<br />
==Fermi architecture==<br />
<br />
==Kepler architecture==<br />
<br />
==Maxwell architecture==<br />
<br />
==Pascal architecture==<br />
<br />
==Volta architecture==<br />
<br />
==Turing architecture: Raytracing and ML==<br />
<br />
==Ampere architecture==<br />
<br />
==Lovelace / Hopper architecture==<br />
<br />
==Blackwell (GB1xx)==<br />
<br />
==Blackwell 2.0 (GB2xx)==<br />
<br />
==Rubin architecture (still in development)==<br />
This is Nvidia's 2026 architecture for GPUs.<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=List_of_GPUs&diff=1711List of GPUs2025-12-31T01:46:36Z<p>Starfrost: </p>
<hr />
<div>This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) often produced dozens of SKUs for a particular "series" and the list would be full of hundreds of almost identical graphics cards.<br />
<br />
==Quadratic texture mappers==<br />
<br />
=== NV0 ===<br />
{{Main|NV0}}<br />
Not actually a GPU, but a series of VxD drivers under Windows 3.x to emulate the NV1 environment before it was ready. <br />
<br />
==== Features ====<br />
* Unknown<br />
<br />
=== NV1 ===<br />
{{Main|NV1}}<br />
<br />
The first GPU (or as it was dubbed by Nvidia at the time, "Multimedia Accelerator") designed by Nvidia and manufactured by SGS-Thomson Microelectronics (now STMicroelectronics), designed starting in 1993 and ending with its release in 1995. Its name is a contraction of "GX Next Version" (GXNV), as the GPU was designed by the same person, Curtis Priem, who designed the Sun GX for graphics workstations; Huang mandated the rename to NV1 for legal reasons. Unlike all later released Nvidia graphics cards, it does not render using triangles as the fundamental basis of graphical rendering but instead by using quad patching to implement quadratic texture mapped (QTM)'d curves. This has advantages for certain applications, such as computer-aided design and smooth curved surfaces, but is much more cumbersome for programming and game engine development, which was the intended market. There are also many other unique features, as Nvidia's strategy at this time was to attempt to monopolise all of the I/O on the graphical hardware. Ultimately it failed, due to its high cost, poor VGA functionality, and poor Direct3D (which was based on graphical hardware), and was discontinued in Q1 of 1996, not long after its launch. Apparently, at least 250,000 chips were sold, but most of them were returned without ever being put into cards due to poor sales; the poor sales also appear to have led to the cancellation of a 350 nm die shrink<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/090904.pdf (Microprocessor Report, July 10, 1995)</ref>.<br />
<br />
The original text (barring some minor redactions) of the "Strategic Collaboration Agreement" to develop the Nvidia NV1, RIVA 128 (NV3) and RIVA 128 ZX (NV3T) with SGS-Thomson can be found in a 1998 SEC filing, as it was an agreement that materially affected investors scoping out the company for potential investment during the IPO process<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref>.<br />
<br />
====Features====<br />
* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw<br />
* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support<br />
* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support<br />
* 3D Quadrilateral and Triangle rendering (however much slower than QTMs and not the primary focus)<br />
* Two-cache Gray-code indexed FIFO, [[PFIFO]] (one, <code>CACHE0</code>, with a size of one; another with 32 total entries) for graphical command ("object" submission)<br />
* Pseudo-C++ object system for total lunacy in design<br />
* Multi-channel DMA engine with 8 DMA channels, each with 8 subchannels (selectable by "context switching"), which can also be written to via PIO (<code>NV_USER</code>)<br />
* Oddly addressed [[RAMIN]] area for object submission<br />
* Hash table ([[RAMHT]]) for further object caching<br />
* Built-in error handling for invalid object submission via sending to [[RAMRO]]<br />
* Notification functionality via DMA into driver memory for GPU to driver communication<br />
* 1 to 4 MB of video memory, which can either be DRAM or VRAM<br />
* External RAMDAC (<code>NVDAC</code>), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU<br />
* Partially emulated VGA compatibility implemented via a separate PCI ID<br />
* Multiple clock sources (<code>VPLL</code> for pixel clock, varying based on resolution and color depth for controlling the CRT, and <code>MPLL</code> for everything else - the card ran at 100Mhz on average)<br />
<br />
This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card: <br />
* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)<br />
* Sega Saturn game port support (in the external DAC)<br />
* Partial VGA compatibility, largely emulated in software<br />
* EEPROM for storage of chip ID<br />
* [[NV1/DRM|Unused hardware-implemented encryption and digital rights management functionality]]<br />
* VESA Local Bus support, as well as PCI (seemingly only PCI versions were released as VLB was relatively short-lived)<br />
* Proprietary NVLIB API to avoid direct hardware programming <br />
<br />
=== NV2 ===<br />
{{Main|NV2}}<br />
The NV2 was a GPU designed under contract from Sega for the "Saturn V08", the first version of the project that became the Sega Dreamcast, starting in May 1995<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref> around the time of the announcement of the NV1. It was cancelled, at some point around early to mid 1996, due to internal pressure from Sega (especially their AM2 division) to move to a triangle-based model, combined with possible intransigence on Nvidia's part. SEGA still paid (loaned then forgave) NVIDIA 5 million dollars, which prevented the company from going bankrupt immediately. Most information on the technical implementation of the NV2 comes from Don Goddard, who was the main employee tasked with programming the NV2 (via a software emulator on the NV1) - which he described as "hella confusing", and with no debugging - at Sega of America.<br />
<br />
====New features====<br />
* Proto-shader microcode similar to the Nintendo 64 Reality Coprocessor & Reality Signal Processor GPU to handle texture compression, lighting, positions, and texture U/V coordinates<br />
* Possibly hardware-accelerated lighting <br />
* Color compression<br />
* Hardware-accelerated Z-buffering<br />
* Cartridge DMA (yes, cartridge) via the <code>PCART</code> subsystem<br />
* No VGA compatibility, as it was a game console GPU<br />
<br />
The status on if the NV2 ever worked as physical hardware is disputed; it was certainly taped out (even if only for one stepping, A0), and failed a demonstration to Sega, which may have triggered the cancellation of the project. However, some sources claim that a single engineer, Wayne Kogachi<ref>''The Nvidia Way'', Tae Kim, page 62</ref>, was assigned to and was successfully able to product a working chip. This was done in order to trigger an $1 million milestone payment, which was required due to the company's zero sales at the time. <br />
<br />
=== NV3 (Quadratic Texture Mapped version) ===<br />
{{Main|NV3 (QTM)}}<br />
<br />
Before [[David Kirk]] was hired at Nvidia, Nvidia were planning to launch a QTM-based "NV3" (entirely separate to the product launched as the Riva 128), a 100% functional superset of NV1 for PCs. It was announced around March 1996<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/100304.pdf (Microprocessor Report, March 5, 1996)</ref> for volume production in October of 1996, and was apparently going to be used in a home theater system by Lexicon, as the audio chip, provide an integrated RAMDAC and be generally much faster. It was most likely cancelled extremely quickly after its announcement, owing to Nvidia's new direction of developing triangle-based graphics accelerators. Very little else is known about it (other than the fact it would apparently be able to process 500,000 50-pixel triangles per second) and the original press release, published on 22 January 1996, does not mention the NV3, but also calls the NV1 NVIDIA's "first generation" product<ref>https://web.archive.org/web/19961112163232/http://www.nvidia.com/corporate/prlexicon.html ("LEXICON AND NVIDIA TEAM UP FOR NEXT GENERATION OF PC ENTERTAINMENT SOUND"; NVIDIA Corporation; 22 January 1996)</ref>. However, it does not seem to be a typo on the part of Microprocessor Report since it is repeated many times and explicitly stated to be a PC graphics card, which the NV2 was not.<br />
<br />
==Fixed function, no T&L (RIVA)==<br />
<br />
=== NV3 (RIVA 128)===<br />
{{Main|NV3}}<br />
[[David Kirk]] left Crystal Dynamics to replace [[Curtis Priem]] as the manager of GPU development at Nvidia after the NV2 was cancelled, and decided that sane design was the best way to go. Across nine months in 1996 and 1997, a triangle-based design was thrown together (completed in approximately January 1997?), tested extensively on a hardware simulator from another nearly-bankrupt company called [[Ikos]] (as Nvidia did not have the money for more than one revision of the chip without sales), and then taped out around 1 April 1997<ref>https://www.wave-report.com/1997%20Wave%20issues/wave707.html#707.4 (WAVE Report, 14 April 1997, "2 weeks out of fab")</ref>. The card was demoed at CGDC 1997, with Direct3D drivers that had only had crash bugs fixed hours before the demo and OpenGL drivers that had only achieved any functionality at all two days earlier<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/qAKzlj9qf5Q/m/lBQ25B1dhJMJ (USENET; "3D Chips at CGDC", Samuel S. Paik, 28 April 1997)</ref>, and were apparently "slow and buggy". The card launched as the "RIVA 128" ('''R'''eal-time '''I'''nteractive '''V'''ideo and '''A'''nimation accelerator, '''128'''-bit bus) in August 1997 (while the earliest known drivers are GDI-only NT 4.0 drivers compiled on 17 July 1997, these seem to have simply been an accidental release of pre-release drivers with an OEM card as they are an extreme outlier, with the earliest Win9x drivers and generic Nvidia drivers dated mid-August). OpenGL drivers were first released in alpha form in December 1997 and full form in March 1998. <br />
<br />
The card was very successful, at least compared to previous models and caused Nvidia's revenue to jump from $5.5 million in the first nine months of 1997 to $23.5 million in the last few months - several million were manufactured. Driver support ended in early 1999 (although 2D-only drivers continued to be compiled for Windows 2000 and XP until 2001) and manufacturing ended some time in mid to late 1999 for the ZX variant.<br />
<br />
====New features====<br />
* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)<br />
* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)<br />
* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)<br />
* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit<br />
* The ability to scale and stretch images while receiving them from system memory (<code>USCALED</code> and <code>USTRTCH</code> objects)<br />
* Generic image upload objects<br />
* AGP 1X bus support<br />
* DMA object submission for 3D<br />
* [[NV3 RMA|Real-Mode Access]], replacing [[NV1 RMC]]<br />
* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability<br />
* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)<br />
* Hardware-accelerated Z-buffering (in a released card)<br />
* Perspective-correct texture mapping (QTMs used forward texture mapping)<br />
* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded<br />
* Hardware-accelerated culling<br />
* Hardware-accelerated alpha buffer (for 3D acceleration)<br />
* Hardware-accelerated specular highlight<br />
* Hardware-accelerated texture offseting (varying the origin point of a texture)<br />
* Hardware fog support with 24-bit colour (vertex fog only)<br />
* Hardware-accelerated color space conversion <br />
* Hardware cursor now supports colour<br />
* Configurable frustum culling modes (clockwise/counterclockwise)<br />
* YUV420 and YUV422 support<br />
* PC-98 support changed to "NEC mode" strap rather than different VBIOS<br />
* Moved to a new 350 nm process rather than 500 nm<br />
* "Mediaport" on-card that allows plugging in external MPEG decoder<br />
* TV-Out support<br />
* RAMDAC and CRTC integrated on-die<br />
<br />
* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine<br />
* VGA and VESA compatibility, licensed from [[Weitek]]<br />
<br />
====Removed features====<br />
* Quadratic texture mapping (QTM) support<br />
* Quad patching more generally<br />
* [[NV1 DRM|Digital rights management]]<br />
* [[NV1 RMC]] (replaced with RMA)<br />
* Sound capability (Revision B and later)<br />
* Sega Saturn gamepad support<br />
* [[NV2]] microcode<br />
* VLB bus support<br />
* 3D capability at resolutions above 960*720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152*864<br />
<br />
=== NV3T (RIVA 128 ZX) ===<br />
{{Main|NV3#NV3T}}<br />
<br />
When Intel announced the Intel i740 GPU, Nvidia got cold feet and decided to rev a new version, revision C, of the RIVA 128, add some minor features, allow for 8 MB of VRAM and rebrand it as a new version.<br />
<br />
====Added features====<br />
* 8 MB of VRAM, rather than just 2 or 4<br />
* 1080p and 1920x1200 resolution support in the BIOS<br />
* PFIFO CACHE1 is now 64 slots deep instead of 32 <br />
* 3D capability at resolutions above 960*720 is possible again<br />
* The ability to write to <code>PSTRAPS</code><br />
* ACPI support (indicated by the PCI device ID changing to <code>0x0019</code>)<br />
* Notifiers to VRAM rather than just the main system RAM (check this)<br />
* Higher RAMDAC clock (260Mhz instead of 205)<br />
** Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)<br />
* AGP 2X bus support<br />
<br />
=== NV4 (RIVA TNT) ===<br />
By April of 1997, revenues were soaring and the future of the company was secured. Therefore, nVIDIA began work on their next generation design, which would have enough time in the oven to be polished and finished on release; large refactors of both the hardware and software platforms used since [[NV1]] were undertaken. Due to this (the NV4 is the first GPU supported by modern-style multi-chip drivers, rather than requiring a separate Resource Manager branch for every single model of hardware), for a very long time (until just before the debut of CUDA) this design was considered to be the "base" level that all other designs extended, with newer GPUs being "NV4 compatible". Despite having to be underclocked quite severely, it was still almost as fast as the Voodoo2 with several serious advantages<br />
<br />
====Added features====<br />
* Up to 16 MB VRAM<br />
* Hardware-accelerated stencil buffering (8-bit); can be interlaced with the Z buffer for higher performance and lower memory bandwidth use ("zeta buffer")<br />
* 16 DMA channels instead of 8<br />
* Pushbuffer-based DMA object submission<br />
** They can be 124 or 512 bytes<br />
* 32-bit 3D rendering<br />
* Dual texture pipes that can rasterise two texels per cycle<br />
* PFIFO CACHE1 is now 128 slots deep instead of 64<br />
* Class system in GPU is now the same as the class system in the Resource Manager<br />
* FIFO timeslice scheduler <br />
* [[NV4 PGRAPH#Colour combiners|Colour combiners]], two proto-shaders that operate on the fragments right before rasterisation - the result of one can be passed into the other.<br />
* Unified memory support for iGPUs<br />
* Some DVD acceleration support (such as support for various DVD colour formats like <code>A4V6YB6A4U6YA6</code>), but I am not sure if it was finished<br />
* Trilinear filtering<br />
* Anisotropic filtering (kind of crappy and approximated)<br />
* Texture swizzling<br />
* Configurable Z buffer format (IEEE 754 float or fixed point)<br />
* Up to 6 buffers<br />
** Ability to swizzle buffers 2 and 5<br />
** Buffers are now optionally part of the MMU with a base and limit<br />
* Somewhat different <code>NvNotification</code> format<br />
* Ability to scramble the framebuffer<br />
* MMIO register to change start of CRTC VGA framebuffer<br />
* Even more debug registers, including ping-pong mode (what??)<br />
* An extremely basic two instruction set DMA bytecode to allow jumping between different parts of DMA streams<br />
* 16bpp modes are now actually 16bpp by default, not 15bpp<br />
* Buffer formats <code>Z8R8G8B8</code>, <code>O1Z7R8G8B8</code> and <code>O1A7R8G8B8</code> for interlacing Z and colour buffers<br />
* YUV buffer formats <code>V8YB8U8YA8</code> and <code>YB8V8YA8U8</code> <br />
* <code>FFINTFC</code> registers for internal state information <br />
* [[Weitek]] CRTC extended sequencer register locking was moved from sequencer register 0x6 to CRTC register 0x1F<br />
** CRTC extended sequencer registers can be unlocked for read or both read and write. In NV3 they can only be unlocked for read and write<br />
* <code>PRAMDAC</code> can output 24 bit colour - the GPU still only works with 8, 16 and 32 bit colour, and it doesn't seem these modes are exposed to the display drivers.<br />
<br />
====Removed features====<br />
* 1 MB VRAM (2 and 4 are actually supported but none were ever made, although 4 MB was announced)<br />
* <code>U*</code> registers. Instead, method information can be obtained via determining which Resource Manager methods are sent to hardware.<br />
* [[NV3 DMA]] mode submission<br />
* PC-98 support<br />
* Microsoft zero-order hold texture (<code>ZOH_MS</code>) coordinate interpolation <br />
* <code>PRAMDAC_GENERAL_CONTROL_565_MODE</code> is removed, replaced with the <code>ALT_MODE</code> bit, which can cause 16bpp to become 15bpp and 32bpp to become 24bpp<br />
<br />
=== NV5 (RIVA TNT2) ===<br />
<br />
==== NV5ULTRA (RIVA TNT2 Ultra) ====<br />
==== NV5VANTA (RIVA TNT2 Vanta; Vanta LT) ====<br />
==== NV6 (RIVA TNT2 M64) ====<br />
<br />
<br />
==Celsius architecture: Fixed function, T&L==<br />
<br />
==Kelvin architecture: Programmable shaders==<br />
<br />
==Rankine architecture==<br />
<br />
==Curie architecture==<br />
<br />
==Tesla architecture: GPGPU, unified shaders and CUDA ==<br />
<br />
==Tesla 2.0 architecture (GT2xx)==<br />
<br />
==Fermi architecture==<br />
<br />
==Kepler architecture==<br />
<br />
==Maxwell architecture==<br />
<br />
==Pascal architecture==<br />
<br />
==Volta architecture==<br />
<br />
==Turing architecture: Raytracing and ML==<br />
<br />
==Ampere architecture==<br />
<br />
==Lovelace / Hopper architecture==<br />
<br />
==Blackwell (GB1xx)==<br />
<br />
==Blackwell 2.0 (GB2xx)==<br />
<br />
==Rubin architecture (still in development)==<br />
This is Nvidia's 2026 architecture for GPUs.<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=List_of_GPUs&diff=1710List of GPUs2025-12-31T01:43:41Z<p>Starfrost: </p>
<hr />
<div>This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) often produced dozens of SKUs for a particular "series" and the list would be full of hundreds of almost identical graphics cards.<br />
<br />
==Quadratic texture mappers==<br />
<br />
=== NV0 ===<br />
{{Main|NV0}}<br />
Not actually a GPU, but a series of VxD drivers under Windows 3.x to emulate the NV1 environment before it was ready. <br />
<br />
==== Features ====<br />
* Unknown<br />
<br />
=== NV1 ===<br />
{{Main|NV1}}<br />
<br />
The first GPU (or as it was dubbed by Nvidia at the time, "Multimedia Accelerator") designed by Nvidia and manufactured by SGS-Thomson Microelectronics (now STMicroelectronics), designed starting in 1993 and ending with its release in 1995. Its name is a contraction of "GX Next Version" (GXNV), as the GPU was designed by the same person, Curtis Priem, who designed the Sun GX for graphics workstations; Huang mandated the rename to NV1 for legal reasons. Unlike all later released Nvidia graphics cards, it does not render using triangles as the fundamental basis of graphical rendering but instead by using quad patching to implement quadratic texture mapped (QTM)'d curves. This has advantages for certain applications, such as computer-aided design and smooth curved surfaces, but is much more cumbersome for programming and game engine development, which was the intended market. There are also many other unique features, as Nvidia's strategy at this time was to attempt to monopolise all of the I/O on the graphical hardware. Ultimately it failed, due to its high cost, poor VGA functionality, and poor Direct3D (which was based on graphical hardware), and was discontinued in Q1 of 1996, not long after its launch. Apparently, at least 250,000 chips were sold, but most of them were returned without ever being put into cards due to poor sales; the poor sales also appear to have led to the cancellation of a 350 nm die shrink<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/090904.pdf (Microprocessor Report, July 10, 1995)</ref>.<br />
<br />
The original text (barring some minor redactions) of the "Strategic Collaboration Agreement" to develop the Nvidia NV1, RIVA 128 (NV3) and RIVA 128 ZX (NV3T) with SGS-Thomson can be found in a 1998 SEC filing, as it was an agreement that materially affected investors scoping out the company for potential investment during the IPO process<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref>.<br />
<br />
====Features====<br />
* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw<br />
* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support<br />
* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support<br />
* 3D Quadrilateral and Triangle rendering (however much slower than QTMs and not the primary focus)<br />
* Two-cache Gray-code indexed FIFO, [[PFIFO]] (one, <code>CACHE0</code>, with a size of one; another with 32 total entries) for graphical command ("object" submission)<br />
* Pseudo-C++ object system for total lunacy in design<br />
* Multi-channel DMA engine with 8 DMA channels, each with 8 subchannels (selectable by "context switching"), which can also be written to via PIO (<code>NV_USER</code>)<br />
* Oddly addressed [[RAMIN]] area for object submission<br />
* Hash table ([[RAMHT]]) for further object caching<br />
* Built-in error handling for invalid object submission via sending to [[RAMRO]]<br />
* Notification functionality via DMA into driver memory for GPU to driver communication<br />
* 1 to 4 MB of video memory, which can either be DRAM or VRAM<br />
* External RAMDAC (<code>NVDAC</code>), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU<br />
* Partially emulated VGA compatibility implemented via a separate PCI ID<br />
* Multiple clock sources (<code>VPLL</code> for pixel clock, varying based on resolution and color depth for controlling the CRT, and <code>MPLL</code> for everything else - the card ran at 100Mhz on average)<br />
<br />
This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card: <br />
* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)<br />
* Sega Saturn game port support (in the external DAC)<br />
* Partial VGA compatibility, largely emulated in software<br />
* EEPROM for storage of chip ID<br />
* [[NV1/DRM|Unused hardware-implemented encryption and digital rights management functionality]]<br />
* VESA Local Bus support, as well as PCI (seemingly only PCI versions were released as VLB was relatively short-lived)<br />
* Proprietary NVLIB API to avoid direct hardware programming <br />
<br />
=== NV2 ===<br />
{{Main|NV2}}<br />
The NV2 was a GPU designed under contract from Sega for the "Saturn V08", the first version of the project that became the Sega Dreamcast, starting in May 1995<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref> around the time of the announcement of the NV1. It was cancelled, at some point around early to mid 1996, due to internal pressure from Sega (especially their AM2 division) to move to a triangle-based model, combined with possible intransigence on Nvidia's part. SEGA still paid (loaned then forgave) NVIDIA 5 million dollars, which prevented the company from going bankrupt immediately. Most information on the technical implementation of the NV2 comes from Don Goddard, who was the main employee tasked with programming the NV2 (via a software emulator on the NV1) - which he described as "hella confusing", and with no debugging - at Sega of America.<br />
<br />
====New features====<br />
* Proto-shader microcode similar to the Nintendo 64 Reality Coprocessor & Reality Signal Processor GPU to handle texture compression, lighting, positions, and texture U/V coordinates<br />
* Possibly hardware-accelerated lighting <br />
* Color compression<br />
* Hardware-accelerated Z-buffering<br />
* Cartridge DMA (yes, cartridge) via the <code>PCART</code> subsystem<br />
* No VGA compatibility, as it was a game console GPU<br />
<br />
The status on if the NV2 ever worked as physical hardware is disputed; it was certainly taped out (even if only for one stepping, A0), and failed a demonstration to Sega, which may have triggered the cancellation of the project. However, some sources claim that a single engineer, Wayne Kogachi<ref>''The Nvidia Way'', Tae Kim, page 62</ref>, was assigned to and was successfully able to product a working chip. This was done in order to trigger an $1 million milestone payment, which was required due to the company's zero sales at the time. <br />
<br />
=== NV3 (Quadratic Texture Mapped version) ===<br />
{{Main|NV3 (QTM)}}<br />
<br />
Before [[David Kirk]] was hired at Nvidia, Nvidia were planning to launch a QTM-based "NV3" (entirely separate to the product launched as the Riva 128), a 100% functional superset of NV1 for PCs. It was announced around March 1996<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/100304.pdf (Microprocessor Report, March 5, 1996)</ref> for volume production in October of 1996, and was apparently going to be used in a home theater system by Lexicon, as the audio chip, provide an integrated RAMDAC and be generally much faster. It was most likely cancelled extremely quickly after its announcement, owing to Nvidia's new direction of developing triangle-based graphics accelerators. Very little else is known about it (other than the fact it would apparently be able to process 500,000 50-pixel triangles per second) and the original press release, published on 22 January 1996, does not mention the NV3, but also calls the NV1 NVIDIA's "first generation" product<ref>https://web.archive.org/web/19961112163232/http://www.nvidia.com/corporate/prlexicon.html ("LEXICON AND NVIDIA TEAM UP FOR NEXT GENERATION OF PC ENTERTAINMENT SOUND"; NVIDIA Corporation; 22 January 1996)</ref>. However, it does not seem to be a typo on the part of Microprocessor Report since it is repeated many times and explicitly stated to be a PC graphics card, which the NV2 was not.<br />
<br />
==Fixed function, no T&L (RIVA)==<br />
<br />
=== NV3 (RIVA 128)===<br />
{{Main|NV3}}<br />
[[David Kirk]] left Crystal Dynamics to replace [[Curtis Priem]] as the manager of GPU development at Nvidia after the NV2 was cancelled, and decided that sane design was the best way to go. Across nine months in 1996 and 1997, a triangle-based design was thrown together (completed in approximately January 1997?), tested extensively on a hardware simulator from another nearly-bankrupt company called [[Ikos]] (as Nvidia did not have the money for more than one revision of the chip without sales), and then taped out around 1 April 1997<ref>https://www.wave-report.com/1997%20Wave%20issues/wave707.html#707.4 (WAVE Report, 14 April 1997, "2 weeks out of fab")</ref>. The card was demoed at CGDC 1997, with Direct3D drivers that had only had crash bugs fixed hours before the demo and OpenGL drivers that had only achieved any functionality at all two days earlier<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/qAKzlj9qf5Q/m/lBQ25B1dhJMJ (USENET; "3D Chips at CGDC", Samuel S. Paik, 28 April 1997)</ref>, and were apparently "slow and buggy". The card launched as the "RIVA 128" ('''R'''eal-time '''I'''nteractive '''V'''ideo and '''A'''nimation accelerator, '''128'''-bit bus) in August 1997 (while the earliest known drivers are GDI-only NT 4.0 drivers compiled on 17 July 1997, these seem to have simply been an accidental release of pre-release drivers with an OEM card as they are an extreme outlier, with the earliest Win9x drivers and generic Nvidia drivers dated mid-August). OpenGL drivers were first released in alpha form in December 1997 and full form in March 1998. <br />
<br />
The card was very successful, at least compared to previous models and caused Nvidia's revenue to jump from $5.5 million in the first nine months of 1997 to $23.5 million in the last few months - several million were manufactured. Driver support ended in early 1999 (although 2D-only drivers continued to be compiled for Windows 2000 and XP until 2001) and manufacturing ended some time in mid to late 1999 for the ZX variant.<br />
<br />
====New features====<br />
* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)<br />
* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)<br />
* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)<br />
* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit<br />
* The ability to scale and stretch images while receiving them from system memory (<code>USCALED</code> and <code>USTRTCH</code> objects)<br />
* Generic image upload objects<br />
* AGP 1X bus support<br />
* DMA object submission for 3D<br />
* [[NV3 RMA|Real-Mode Access]], replacing [[NV1 RMC]]<br />
* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability<br />
* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)<br />
* Hardware-accelerated Z-buffering (in a released card)<br />
* Perspective-correct texture mapping (QTMs used forward texture mapping)<br />
* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded<br />
* Hardware-accelerated culling<br />
* Hardware-accelerated alpha buffer (for 3D acceleration)<br />
* Hardware-accelerated specular highlight<br />
* Hardware-accelerated texture offseting (varying the origin point of a texture)<br />
* Hardware fog support with 24-bit colour (vertex fog only)<br />
* Hardware-accelerated color space conversion <br />
* Hardware cursor now supports colour<br />
* Configurable frustum culling modes (clockwise/counterclockwise)<br />
* YUV420 and YUV422 support<br />
* PC-98 support changed to "NEC mode" strap rather than different VBIOS<br />
* Moved to a new 350 nm process rather than 500 nm<br />
* "Mediaport" on-card that allows plugging in external MPEG decoder<br />
* TV-Out support<br />
* RAMDAC and CRTC integrated on-die<br />
<br />
* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine<br />
* VGA and VESA compatibility, licensed from [[Weitek]]<br />
<br />
====Removed features====<br />
* Quadratic texture mapping (QTM) support<br />
* Quad patching more generally<br />
* [[NV1 DRM|Digital rights management]]<br />
* [[NV1 RMC]] (replaced with RMA)<br />
* Sound capability (Revision B and later)<br />
* Sega Saturn gamepad support<br />
* [[NV2]] microcode<br />
* VLB bus support<br />
* 3D capability at resolutions above 960*720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152*864<br />
<br />
=== NV3T (RIVA 128 ZX) ===<br />
{{Main|NV3#NV3T}}<br />
<br />
When Intel announced the Intel i740 GPU, Nvidia got cold feet and decided to rev a new version, revision C, of the RIVA 128, add some minor features, allow for 8 MB of VRAM and rebrand it as a new version.<br />
<br />
====Added features====<br />
* 8 MB of VRAM, rather than just 2 or 4<br />
* 1080p and 1920x1200 resolution support in the BIOS<br />
* PFIFO CACHE1 is now 64 slots deep instead of 32 <br />
* 3D capability at resolutions above 960*720 is possible again<br />
* The ability to write to <code>PSTRAPS</code><br />
* ACPI support (indicated by the PCI device ID changing to <code>0x0019</code>)<br />
* Notifiers to VRAM rather than just the main system RAM (check this)<br />
* Higher RAMDAC clock (260Mhz instead of 205)<br />
** Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)<br />
* AGP 2X bus support<br />
<br />
=== NV4 (RIVA TNT) ===<br />
By April of 1997, revenues were soaring and the future of the company was secured. Therefore, nVIDIA began work on their next generation design, which would have enough time in the oven to be polished and finished on release; large refactors of both the hardware and software platforms used since [[NV1]] were undertaken. Due to this (the NV4 is the first GPU supported by modern-style multi-chip drivers, rather than requiring a separate Resource Manager branch for every single model of hardware), for a very long time (until just before the debut of CUDA) this design was considered to be the "base" level that all other designs extended, with newer GPUs being "NV4 compatible". Despite having to be underclocked quite severely, it was still almost as fast as the Voodoo2 with several serious advantages<br />
<br />
====Added features====<br />
* Up to 16 MB VRAM<br />
* Hardware-accelerated stencil buffering (8-bit); can be interlaced with the Z buffer for higher performance and lower memory bandwidth use ("zeta buffer")<br />
* 16 DMA channels instead of 8<br />
* Pushbuffer-based DMA object submission<br />
** They can be 124 or 512 bytes<br />
* 32-bit 3D rendering<br />
* Dual texture pipes that can rasterise two texels per cycle<br />
* PFIFO CACHE1 is now 128 slots deep instead of 64<br />
* Class system in GPU is now the same as the class system in the Resource Manager<br />
* FIFO timeslice scheduler <br />
* [[NV4 PGRAPH#Colour combiners|Colour combiners]], two proto-shaders that operate on the fragments right before rasterisation - the result of one can be passed into the other.<br />
* Unified memory support for iGPUs<br />
* Some DVD acceleration support (such as support for various DVD colour formats like <code>A4V6YB6A4U6YA6</code>), but I am not sure if it was finished<br />
* Trilinear filtering<br />
* Anisotropic filtering (kind of crappy and approximated)<br />
* Texture swizzling<br />
* Configurable Z buffer format (IEEE 754 float or fixed point)<br />
* Up to 6 buffers<br />
** Ability to swizzle buffers 2 and 5<br />
** Buffers are now optionally part of the MMU with a base and limit<br />
* Somewhat different <code>NvNotification</code> format<br />
* Ability to scramble the framebuffer<br />
* MMIO register to change start of CRTC VGA framebuffer<br />
* Even more debug registers, including ping-pong mode (what??)<br />
* An extremely basic two instruction set DMA bytecode to allow jumping between different parts of DMA streams<br />
* 16bpp modes are now actually 16bpp by default, not 15bpp<br />
* Buffer formats <code>Z8R8G8B8</code>, <code>O1Z7R8G8B8</code> and <code>O1A7R8G8B8</code> for interlacing Z and colour buffers<br />
* YUV buffer formats <code>V8YB8U8YA8</code> and <code>YB8V8YA8U8</code> <br />
* <code>FFINTFC</code> registers for internal state information <br />
* [[Weitek]] CRTC extended sequencer register locking was moved from sequencer register 0x6 to CRTC register 0x1F<br />
** CRTC extended sequencer registers can be unlocked for read or both read and write. In NV3 they can only be unlocked for read and write<br />
<br />
====Removed features====<br />
* 1 MB VRAM (2 and 4 are actually supported but none were ever made, although 4 MB was announced)<br />
* <code>U*</code> registers. Instead, method information can be obtained via determining which Resource Manager methods are sent to hardware.<br />
* [[NV3 DMA]] mode submission<br />
* PC-98 support<br />
* Microsoft zero-order hold texture (<code>ZOH_MS</code>) coordinate interpolation <br />
<br />
=== NV5 (RIVA TNT2) ===<br />
<br />
==== NV5ULTRA (RIVA TNT2 Ultra) ====<br />
==== NV5VANTA (RIVA TNT2 Vanta; Vanta LT) ====<br />
==== NV6 (RIVA TNT2 M64) ====<br />
<br />
<br />
==Celsius architecture: Fixed function, T&L==<br />
<br />
==Kelvin architecture: Programmable shaders==<br />
<br />
==Rankine architecture==<br />
<br />
==Curie architecture==<br />
<br />
==Tesla architecture: GPGPU, unified shaders and CUDA ==<br />
<br />
==Tesla 2.0 architecture (GT2xx)==<br />
<br />
==Fermi architecture==<br />
<br />
==Kepler architecture==<br />
<br />
==Maxwell architecture==<br />
<br />
==Pascal architecture==<br />
<br />
==Volta architecture==<br />
<br />
==Turing architecture: Raytracing and ML==<br />
<br />
==Ampere architecture==<br />
<br />
==Lovelace / Hopper architecture==<br />
<br />
==Blackwell (GB1xx)==<br />
<br />
==Blackwell 2.0 (GB2xx)==<br />
<br />
==Rubin architecture (still in development)==<br />
This is Nvidia's 2026 architecture for GPUs.<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=List_of_GPUs&diff=1709List of GPUs2025-12-31T01:43:03Z<p>Starfrost: </p>
<hr />
<div>This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) often produced dozens of SKUs for a particular "series" and the list would be full of hundreds of almost identical graphics cards.<br />
<br />
==Quadratic texture mappers==<br />
<br />
=== NV0 ===<br />
{{Main|NV0}}<br />
Not actually a GPU, but a series of VxD drivers under Windows 3.x to emulate the NV1 environment before it was ready. <br />
<br />
==== Features ====<br />
* Unknown<br />
<br />
=== NV1 ===<br />
{{Main|NV1}}<br />
<br />
The first GPU (or as it was dubbed by Nvidia at the time, "Multimedia Accelerator") designed by Nvidia and manufactured by SGS-Thomson Microelectronics (now STMicroelectronics), designed starting in 1993 and ending with its release in 1995. Its name is a contraction of "GX Next Version" (GXNV), as the GPU was designed by the same person, Curtis Priem, who designed the Sun GX for graphics workstations; Huang mandated the rename to NV1 for legal reasons. Unlike all later released Nvidia graphics cards, it does not render using triangles as the fundamental basis of graphical rendering but instead by using quad patching to implement quadratic texture mapped (QTM)'d curves. This has advantages for certain applications, such as computer-aided design and smooth curved surfaces, but is much more cumbersome for programming and game engine development, which was the intended market. There are also many other unique features, as Nvidia's strategy at this time was to attempt to monopolise all of the I/O on the graphical hardware. Ultimately it failed, due to its high cost, poor VGA functionality, and poor Direct3D (which was based on graphical hardware), and was discontinued in Q1 of 1996, not long after its launch. Apparently, at least 250,000 chips were sold, but most of them were returned without ever being put into cards due to poor sales; the poor sales also appear to have led to the cancellation of a 350 nm die shrink<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/090904.pdf (Microprocessor Report, July 10, 1995)</ref>.<br />
<br />
The original text (barring some minor redactions) of the "Strategic Collaboration Agreement" to develop the Nvidia NV1, RIVA 128 (NV3) and RIVA 128 ZX (NV3T) with SGS-Thomson can be found in a 1998 SEC filing, as it was an agreement that materially affected investors scoping out the company for potential investment during the IPO process<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref>.<br />
<br />
====Features====<br />
* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw<br />
* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support<br />
* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support<br />
* 3D Quadrilateral and Triangle rendering (however much slower than QTMs and not the primary focus)<br />
* Two-cache Gray-code indexed FIFO, [[PFIFO]] (one, <code>CACHE0</code>, with a size of one; another with 32 total entries) for graphical command ("object" submission)<br />
* Pseudo-C++ object system for total lunacy in design<br />
* Multi-channel DMA engine with 8 DMA channels, each with 8 subchannels (selectable by "context switching"), which can also be written to via PIO (<code>NV_USER</code>)<br />
* Oddly addressed [[RAMIN]] area for object submission<br />
* Hash table ([[RAMHT]]) for further object caching<br />
* Built-in error handling for invalid object submission via sending to [[RAMRO]]<br />
* Notification functionality via DMA into driver memory for GPU to driver communication<br />
* 1 to 4 MB of video memory, which can either be DRAM or VRAM<br />
* External RAMDAC (<code>NVDAC</code>), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU<br />
* Partially emulated VGA compatibility implemented via a separate PCI ID<br />
* Multiple clock sources (<code>VPLL</code> for pixel clock, varying based on resolution and color depth for controlling the CRT, and <code>MPLL</code> for everything else - the card ran at 100Mhz on average)<br />
<br />
This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card: <br />
* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)<br />
* Sega Saturn game port support (in the external DAC)<br />
* Partial VGA compatibility, largely emulated in software<br />
* EEPROM for storage of chip ID<br />
* [[NV1/DRM|Unused hardware-implemented encryption and digital rights management functionality]]<br />
* VESA Local Bus support, as well as PCI (seemingly only PCI versions were released as VLB was relatively short-lived)<br />
* Proprietary NVLIB API to avoid direct hardware programming <br />
<br />
=== NV2 ===<br />
{{Main|NV2}}<br />
The NV2 was a GPU designed under contract from Sega for the "Saturn V08", the first version of the project that became the Sega Dreamcast, starting in May 1995<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref> around the time of the announcement of the NV1. It was cancelled, at some point around early to mid 1996, due to internal pressure from Sega (especially their AM2 division) to move to a triangle-based model, combined with possible intransigence on Nvidia's part. SEGA still paid (loaned then forgave) NVIDIA 5 million dollars, which prevented the company from going bankrupt immediately. Most information on the technical implementation of the NV2 comes from Don Goddard, who was the main employee tasked with programming the NV2 (via a software emulator on the NV1) - which he described as "hella confusing", and with no debugging - at Sega of America.<br />
<br />
====New features====<br />
* Proto-shader microcode similar to the Nintendo 64 Reality Coprocessor & Reality Signal Processor GPU to handle texture compression, lighting, positions, and texture U/V coordinates<br />
* Possibly hardware-accelerated lighting <br />
* Color compression<br />
* Hardware-accelerated Z-buffering<br />
* Cartridge DMA (yes, cartridge) via the <code>PCART</code> subsystem<br />
* No VGA compatibility, as it was a game console GPU<br />
<br />
The status on if the NV2 ever worked as physical hardware is disputed; it was certainly taped out (even if only for one stepping, A0), and failed a demonstration to Sega, which may have triggered the cancellation of the project. However, some sources claim that a single engineer, Wayne Kogachi<ref>''The Nvidia Way'', Tae Kim, page 62</ref>, was assigned to and was successfully able to product a working chip. This was done in order to trigger an $1 million milestone payment, which was required due to the company's zero sales at the time. <br />
<br />
=== NV3 (Quadratic Texture Mapped version) ===<br />
{{Main|NV3 (QTM)}}<br />
<br />
Before [[David Kirk]] was hired at Nvidia, Nvidia were planning to launch a QTM-based "NV3" (entirely separate to the product launched as the Riva 128), a 100% functional superset of NV1 for PCs. It was announced around March 1996<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/100304.pdf (Microprocessor Report, March 5, 1996)</ref> for volume production in October of 1996, and was apparently going to be used in a home theater system by Lexicon, as the audio chip, provide an integrated RAMDAC and be generally much faster. It was most likely cancelled extremely quickly after its announcement, owing to Nvidia's new direction of developing triangle-based graphics accelerators. Very little else is known about it (other than the fact it would apparently be able to process 500,000 50-pixel triangles per second) and the original press release, published on 22 January 1996, does not mention the NV3, but also calls the NV1 NVIDIA's "first generation" product<ref>https://web.archive.org/web/19961112163232/http://www.nvidia.com/corporate/prlexicon.html ("LEXICON AND NVIDIA TEAM UP FOR NEXT GENERATION OF PC ENTERTAINMENT SOUND"; NVIDIA Corporation; 22 January 1996)</ref>. However, it does not seem to be a typo on the part of Microprocessor Report since it is repeated many times and explicitly stated to be a PC graphics card, which the NV2 was not.<br />
<br />
==Fixed function, no T&L (RIVA)==<br />
<br />
=== NV3 (RIVA 128)===<br />
{{Main|NV3}}<br />
[[David Kirk]] left Crystal Dynamics to replace [[Curtis Priem]] as the manager of GPU development at Nvidia after the NV2 was cancelled, and decided that sane design was the best way to go. Across nine months in 1996 and 1997, a triangle-based design was thrown together (completed in approximately January 1997?), tested extensively on a hardware simulator from another nearly-bankrupt company called [[Ikos]] (as Nvidia did not have the money for more than one revision of the chip without sales), and then taped out around 1 April 1997<ref>https://www.wave-report.com/1997%20Wave%20issues/wave707.html#707.4 (WAVE Report, 14 April 1997, "2 weeks out of fab")</ref>. The card was demoed at CGDC 1997, with Direct3D drivers that had only had crash bugs fixed hours before the demo and OpenGL drivers that had only achieved any functionality at all two days earlier<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/qAKzlj9qf5Q/m/lBQ25B1dhJMJ (USENET; "3D Chips at CGDC", Samuel S. Paik, 28 April 1997)</ref>, and were apparently "slow and buggy". The card launched as the "RIVA 128" ('''R'''eal-time '''I'''nteractive '''V'''ideo and '''A'''nimation accelerator, '''128'''-bit bus) in August 1997 (while the earliest known drivers are GDI-only NT 4.0 drivers compiled on 17 July 1997, these seem to have simply been an accidental release of pre-release drivers with an OEM card as they are an extreme outlier, with the earliest Win9x drivers and generic Nvidia drivers dated mid-August). OpenGL drivers were first released in alpha form in December 1997 and full form in March 1998. <br />
<br />
The card was very successful, at least compared to previous models and caused Nvidia's revenue to jump from $5.5 million in the first nine months of 1997 to $23.5 million in the last few months - several million were manufactured. Driver support ended in early 1999 (although 2D-only drivers continued to be compiled for Windows 2000 and XP until 2001) and manufacturing ended some time in mid to late 1999 for the ZX variant.<br />
<br />
====New features====<br />
* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)<br />
* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)<br />
* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)<br />
* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit<br />
* The ability to scale and stretch images while receiving them from system memory (<code>USCALED</code> and <code>USTRTCH</code> objects)<br />
* Generic image upload objects<br />
* AGP 1X bus support<br />
* DMA object submission for 3D<br />
* [[NV3 RMA|Real-Mode Access]], replacing [[NV1 RMC]]<br />
* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability<br />
* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)<br />
* Hardware-accelerated Z-buffering (in a released card)<br />
* Perspective-correct texture mapping (QTMs used forward texture mapping)<br />
* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded<br />
* Hardware-accelerated culling<br />
* Hardware-accelerated alpha buffer (for 3D acceleration)<br />
* Hardware-accelerated specular highlight<br />
* Hardware-accelerated texture offseting (varying the origin point of a texture)<br />
* Hardware fog support with 24-bit colour (vertex fog only)<br />
* Hardware-accelerated color space conversion <br />
* Hardware cursor now supports colour<br />
* Configurable frustum culling modes (clockwise/counterclockwise)<br />
* YUV420 and YUV422 support<br />
* PC-98 support changed to "NEC mode" strap rather than different VBIOS<br />
* Moved to a new 350 nm process rather than 500 nm<br />
* "Mediaport" on-card that allows plugging in external MPEG decoder<br />
* TV-Out support<br />
* RAMDAC and CRTC integrated on-die<br />
<br />
* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine<br />
* VGA and VESA compatibility, licensed from [[Weitek]]<br />
<br />
====Removed features====<br />
* Quadratic texture mapping (QTM) support<br />
* Quad patching more generally<br />
* [[NV1 DRM|Digital rights management]]<br />
* [[NV1 RMC]] (replaced with RMA)<br />
* Sound capability (Revision B and later)<br />
* Sega Saturn gamepad support<br />
* [[NV2]] microcode<br />
* VLB bus support<br />
* 3D capability at resolutions above 960*720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152*864<br />
<br />
=== NV3T (RIVA 128 ZX) ===<br />
{{Main|NV3#NV3T}}<br />
<br />
When Intel announced the Intel i740 GPU, Nvidia got cold feet and decided to rev a new version, revision C, of the RIVA 128, add some minor features, allow for 8 MB of VRAM and rebrand it as a new version.<br />
<br />
====Added features====<br />
* 8 MB of VRAM, rather than just 2 or 4<br />
* 1080p and 1920x1200 resolution support in the BIOS<br />
* PFIFO CACHE1 is now 64 slots deep instead of 32 <br />
* 3D capability at resolutions above 960*720 is possible again<br />
* The ability to write to <code>PSTRAPS</code><br />
* ACPI support (indicated by the PCI device ID changing to <code>0x0019/code>)<br />
* Notifiers to VRAM rather than just the main system RAM (check this)<br />
* Higher RAMDAC clock (260Mhz instead of 205)<br />
** Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)<br />
* AGP 2X bus support<br />
<br />
=== NV4 (RIVA TNT) ===<br />
By April of 1997, revenues were soaring and the future of the company was secured. Therefore, nVIDIA began work on their next generation design, which would have enough time in the oven to be polished and finished on release; large refactors of both the hardware and software platforms used since [[NV1]] were undertaken. Due to this (the NV4 is the first GPU supported by modern-style multi-chip drivers, rather than requiring a separate Resource Manager branch for every single model of hardware), for a very long time (until just before the debut of CUDA) this design was considered to be the "base" level that all other designs extended, with newer GPUs being "NV4 compatible". Despite having to be underclocked quite severely, it was still almost as fast as the Voodoo2 with several serious advantages<br />
<br />
====Added features====<br />
* Up to 16 MB VRAM<br />
* Hardware-accelerated stencil buffering (8-bit); can be interlaced with the Z buffer for higher performance and lower memory bandwidth use ("zeta buffer")<br />
* 16 DMA channels instead of 8<br />
* Pushbuffer-based DMA object submission<br />
** They can be 124 or 512 bytes<br />
* 32-bit 3D rendering<br />
* Dual texture pipes that can rasterise two texels per cycle<br />
* PFIFO CACHE1 is now 128 slots deep instead of 64<br />
* Class system in GPU is now the same as the class system in the Resource Manager<br />
* FIFO timeslice scheduler <br />
* [[NV4 PGRAPH#Colour combiners|Colour combiners]], two proto-shaders that operate on the fragments right before rasterisation - the result of one can be passed into the other.<br />
* Unified memory support for iGPUs<br />
* Some DVD acceleration support (such as support for various DVD colour formats like <code>A4V6YB6A4U6YA6</code>), but I am not sure if it was finished<br />
* Trilinear filtering<br />
* Anisotropic filtering (kind of crappy and approximated)<br />
* Texture swizzling<br />
* Configurable Z buffer format (IEEE 754 float or fixed point)<br />
* Up to 6 buffers<br />
** Ability to swizzle buffers 2 and 5<br />
** Buffers are now optionally part of the MMU with a base and limit<br />
* Somewhat different <code>NvNotification</code> format<br />
* Ability to scramble the framebuffer<br />
* MMIO register to change start of CRTC VGA framebuffer<br />
* Even more debug registers, including ping-pong mode (what??)<br />
* An extremely basic two instruction set DMA bytecode to allow jumping between different parts of DMA streams<br />
* 16bpp modes are now actually 16bpp by default, not 15bpp<br />
* Buffer formats <code>Z8R8G8B8</code>, <code>O1Z7R8G8B8</code> and <code>O1A7R8G8B8</code> for interlacing Z and colour buffers<br />
* YUV buffer formats <code>V8YB8U8YA8</code> and <code>YB8V8YA8U8</code> <br />
* <code>FFINTFC</code> registers for internal state information <br />
* [[Weitek]] CRTC extended sequencer register locking was moved from sequencer register 0x6 to CRTC register 0x1F<br />
** CRTC extended sequencer registers can be unlocked for read or both read and write. In NV3 they can only be unlocked for read and write<br />
<br />
====Removed features====<br />
* 1 MB VRAM (2 and 4 are actually supported but none were ever made, although 4 MB was announced)<br />
* <code>U*</code> registers. Instead, method information can be obtained via determining which Resource Manager methods are sent to hardware.<br />
* [[NV3 DMA]] mode submission<br />
* PC-98 support<br />
* Microsoft zero-order hold texture (<code>ZOH_MS</code>) coordinate interpolation <br />
<br />
=== NV5 (RIVA TNT2) ===<br />
<br />
==== NV5ULTRA (RIVA TNT2 Ultra) ====<br />
==== NV5VANTA (RIVA TNT2 Vanta; Vanta LT) ====<br />
==== NV6 (RIVA TNT2 M64) ====<br />
<br />
<br />
==Celsius architecture: Fixed function, T&L==<br />
<br />
==Kelvin architecture: Programmable shaders==<br />
<br />
==Rankine architecture==<br />
<br />
==Curie architecture==<br />
<br />
==Tesla architecture: GPGPU, unified shaders and CUDA ==<br />
<br />
==Tesla 2.0 architecture (GT2xx)==<br />
<br />
==Fermi architecture==<br />
<br />
==Kepler architecture==<br />
<br />
==Maxwell architecture==<br />
<br />
==Pascal architecture==<br />
<br />
==Volta architecture==<br />
<br />
==Turing architecture: Raytracing and ML==<br />
<br />
==Ampere architecture==<br />
<br />
==Lovelace / Hopper architecture==<br />
<br />
==Blackwell (GB1xx)==<br />
<br />
==Blackwell 2.0 (GB2xx)==<br />
<br />
==Rubin architecture (still in development)==<br />
This is Nvidia's 2026 architecture for GPUs.<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=List_of_GPUs&diff=1708List of GPUs2025-12-27T14:59:12Z<p>Starfrost: </p>
<hr />
<div>This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) often produced dozens of SKUs for a particular "series" and the list would be full of hundreds of almost identical graphics cards.<br />
<br />
==Quadratic texture mappers==<br />
<br />
=== NV0 ===<br />
{{Main|NV0}}<br />
Not actually a GPU, but a series of VxD drivers under Windows 3.x to emulate the NV1 environment before it was ready. <br />
<br />
==== Features ====<br />
* Unknown<br />
<br />
=== NV1 ===<br />
{{Main|NV1}}<br />
<br />
The first GPU (or as it was dubbed by Nvidia at the time, "Multimedia Accelerator") designed by Nvidia and manufactured by SGS-Thomson Microelectronics (now STMicroelectronics), designed starting in 1993 and ending with its release in 1995. Its name is a contraction of "GX Next Version" (GXNV), as the GPU was designed by the same person, Curtis Priem, who designed the Sun GX for graphics workstations; Huang mandated the rename to NV1 for legal reasons. Unlike all later released Nvidia graphics cards, it does not render using triangles as the fundamental basis of graphical rendering but instead by using quad patching to implement quadratic texture mapped (QTM)'d curves. This has advantages for certain applications, such as computer-aided design and smooth curved surfaces, but is much more cumbersome for programming and game engine development, which was the intended market. There are also many other unique features, as Nvidia's strategy at this time was to attempt to monopolise all of the I/O on the graphical hardware. Ultimately it failed, due to its high cost, poor VGA functionality, and poor Direct3D (which was based on graphical hardware), and was discontinued in Q1 of 1996, not long after its launch. Apparently, at least 250,000 chips were sold, but most of them were returned without ever being put into cards due to poor sales; the poor sales also appear to have led to the cancellation of a 350 nm die shrink<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/090904.pdf (Microprocessor Report, July 10, 1995)</ref>.<br />
<br />
The original text (barring some minor redactions) of the "Strategic Collaboration Agreement" to develop the Nvidia NV1, RIVA 128 (NV3) and RIVA 128 ZX (NV3T) with SGS-Thomson can be found in a 1998 SEC filing, as it was an agreement that materially affected investors scoping out the company for potential investment during the IPO process<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref>.<br />
<br />
====Features====<br />
* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw<br />
* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support<br />
* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support<br />
* 3D Quadrilateral and Triangle rendering (however much slower than QTMs and not the primary focus)<br />
* Two-cache Gray-code indexed FIFO, [[PFIFO]] (one, <code>CACHE0</code>, with a size of one; another with 32 total entries) for graphical command ("object" submission)<br />
* Pseudo-C++ object system for total lunacy in design<br />
* Multi-channel DMA engine with 8 DMA channels, each with 8 subchannels (selectable by "context switching"), which can also be written to via PIO (<code>NV_USER</code>)<br />
* Oddly addressed [[RAMIN]] area for object submission<br />
* Hash table ([[RAMHT]]) for further object caching<br />
* Built-in error handling for invalid object submission via sending to [[RAMRO]]<br />
* Notification functionality via DMA into driver memory for GPU to driver communication<br />
* 1 to 4 MB of video memory, which can either be DRAM or VRAM<br />
* External RAMDAC (<code>NVDAC</code>), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU<br />
* Partially emulated VGA compatibility implemented via a separate PCI ID<br />
* Multiple clock sources (<code>VPLL</code> for pixel clock, varying based on resolution and color depth for controlling the CRT, and <code>MPLL</code> for everything else - the card ran at 100Mhz on average)<br />
<br />
This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card: <br />
* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)<br />
* Sega Saturn game port support (in the external DAC)<br />
* Partial VGA compatibility, largely emulated in software<br />
* EEPROM for storage of chip ID<br />
* [[NV1/DRM|Unused hardware-implemented encryption and digital rights management functionality]]<br />
* VESA Local Bus support, as well as PCI (seemingly only PCI versions were released as VLB was relatively short-lived)<br />
* Proprietary NVLIB API to avoid direct hardware programming <br />
<br />
=== NV2 ===<br />
{{Main|NV2}}<br />
The NV2 was a GPU designed under contract from Sega for the "Saturn V08", the first version of the project that became the Sega Dreamcast, starting in May 1995<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref> around the time of the announcement of the NV1. It was cancelled, at some point around early to mid 1996, due to internal pressure from Sega (especially their AM2 division) to move to a triangle-based model, combined with possible intransigence on Nvidia's part. SEGA still paid (loaned then forgave) NVIDIA 5 million dollars, which prevented the company from going bankrupt immediately. Most information on the technical implementation of the NV2 comes from Don Goddard, who was the main employee tasked with programming the NV2 (via a software emulator on the NV1) - which he described as "hella confusing", and with no debugging - at Sega of America.<br />
<br />
====New features====<br />
* Proto-shader microcode similar to the Nintendo 64 Reality Coprocessor & Reality Signal Processor GPU to handle texture compression, lighting, positions, and texture U/V coordinates<br />
* Possibly hardware-accelerated lighting <br />
* Color compression<br />
* Hardware-accelerated Z-buffering<br />
* Cartridge DMA (yes, cartridge) via the <code>PCART</code> subsystem<br />
* No VGA compatibility, as it was a game console GPU<br />
<br />
The status on if the NV2 ever worked as physical hardware is disputed; it was certainly taped out (even if only for one stepping, A0), and failed a demonstration to Sega, which may have triggered the cancellation of the project. However, some sources claim that a single engineer, Wayne Kogachi<ref>''The Nvidia Way'', Tae Kim, page 62</ref>, was assigned to and was successfully able to product a working chip. This was done in order to trigger an $1 million milestone payment, which was required due to the company's zero sales at the time. <br />
<br />
=== NV3 (Quadratic Texture Mapped version) ===<br />
{{Main|NV3 (QTM)}}<br />
<br />
Before [[David Kirk]] was hired at Nvidia, Nvidia were planning to launch a QTM-based "NV3" (entirely separate to the product launched as the Riva 128), a 100% functional superset of NV1 for PCs. It was announced around March 1996<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/100304.pdf (Microprocessor Report, March 5, 1996)</ref> for volume production in October of 1996, and was apparently going to be used in a home theater system by Lexicon, as the audio chip, provide an integrated RAMDAC and be generally much faster. It was most likely cancelled extremely quickly after its announcement, owing to Nvidia's new direction of developing triangle-based graphics accelerators. Very little else is known about it (other than the fact it would apparently be able to process 500,000 50-pixel triangles per second) and the original press release, published on 22 January 1996, does not mention the NV3, but also calls the NV1 NVIDIA's "first generation" product<ref>https://web.archive.org/web/19961112163232/http://www.nvidia.com/corporate/prlexicon.html ("LEXICON AND NVIDIA TEAM UP FOR NEXT GENERATION OF PC ENTERTAINMENT SOUND"; NVIDIA Corporation; 22 January 1996)</ref>. However, it does not seem to be a typo on the part of Microprocessor Report since it is repeated many times and explicitly stated to be a PC graphics card, which the NV2 was not.<br />
<br />
==Fixed function, no T&L (RIVA)==<br />
<br />
=== NV3 (RIVA 128)===<br />
{{Main|NV3}}<br />
[[David Kirk]] left Crystal Dynamics to replace [[Curtis Priem]] as the manager of GPU development at Nvidia after the NV2 was cancelled, and decided that sane design was the best way to go. Across nine months in 1996 and 1997, a triangle-based design was thrown together (completed in approximately January 1997?), tested extensively on a hardware simulator from another nearly-bankrupt company called [[Ikos]] (as Nvidia did not have the money for more than one revision of the chip without sales), and then taped out around 1 April 1997<ref>https://www.wave-report.com/1997%20Wave%20issues/wave707.html#707.4 (WAVE Report, 14 April 1997, "2 weeks out of fab")</ref>. The card was demoed at CGDC 1997, with Direct3D drivers that had only had crash bugs fixed hours before the demo and OpenGL drivers that had only achieved any functionality at all two days earlier<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/qAKzlj9qf5Q/m/lBQ25B1dhJMJ (USENET; "3D Chips at CGDC", Samuel S. Paik, 28 April 1997)</ref>, and were apparently "slow and buggy". The card launched as the "RIVA 128" ('''R'''eal-time '''I'''nteractive '''V'''ideo and '''A'''nimation accelerator, '''128'''-bit bus) in August 1997 (while the earliest known drivers are GDI-only NT 4.0 drivers compiled on 17 July 1997, these seem to have simply been an accidental release of pre-release drivers with an OEM card as they are an extreme outlier, with the earliest Win9x drivers and generic Nvidia drivers dated mid-August). OpenGL drivers were first released in alpha form in December 1997 and full form in March 1998. <br />
<br />
The card was very successful, at least compared to previous models and caused Nvidia's revenue to jump from $5.5 million in the first nine months of 1997 to $23.5 million in the last few months - several million were manufactured. Driver support ended in early 1999 (although 2D-only drivers continued to be compiled for Windows 2000 and XP until 2001) and manufacturing ended some time in mid to late 1999 for the ZX variant.<br />
<br />
====New features====<br />
* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)<br />
* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)<br />
* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)<br />
* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit<br />
* The ability to scale and stretch images while receiving them from system memory (`USCALED` and `USTRTCH` objects)<br />
* Generic image upload objects<br />
* AGP 1X bus support<br />
* DMA object submission for 3D<br />
* [[NV3 RMA|Real-Mode Access]], replacing [[NV1 RMC]]<br />
* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability<br />
* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)<br />
* Hardware-accelerated Z-buffering (in a released card)<br />
* Perspective-correct texture mapping (QTMs used forward texture mapping)<br />
* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded<br />
* Hardware-accelerated culling<br />
* Hardware-accelerated alpha buffer (for 3D acceleration)<br />
* Hardware-accelerated specular highlight<br />
* Hardware-accelerated texture offseting (varying the origin point of a texture)<br />
* Hardware fog support with 24-bit colour (vertex fog only)<br />
* Hardware-accelerated color space conversion <br />
* Hardware cursor now supports colour<br />
* YUV420 and YUV422 support<br />
* PC-98 support ("NEC mode")<br />
* Moved to a new 350 nm process rather than 500 nm<br />
* "Mediaport" on-card that allows plugging in external MPEG decoder<br />
* TV-Out support<br />
* RAMDAC and CRTC integrated on-die<br />
<br />
* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine<br />
* VGA and VESA compatibility, licensed from [[Weitek]]<br />
<br />
====Removed features====<br />
* Quadratic texture mapping (QTM) support<br />
* Quad patching more generally<br />
* [[NV1 DRM|Digital rights management]]<br />
* [[NV1 RMC]] (replaced with RMA)<br />
* Sound capability (Revision B and later)<br />
* Sega Saturn gamepad support<br />
* [[NV2]] microcode<br />
* VLB bus support<br />
* 3D capability at resolutions above 960*720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152*864<br />
<br />
=== NV3T (RIVA 128 ZX) ===<br />
{{Main|NV3#NV3T}}<br />
<br />
When Intel announced the Intel i740 GPU, Nvidia got cold feet and decided to rev a new version, revision C, of the RIVA 128, add some minor features, allow for 8 MB of VRAM and rebrand it as a new version.<br />
<br />
====Added features====<br />
* 8 MB of VRAM, rather than just 2 or 4<br />
* 1080p and 1920x1200 resolution support in the BIOS<br />
* PFIFO CACHE1 is now 64 slots deep instead of 32 <br />
* 3D capability at resolutions above 960*720 is better again<br />
* The ability to write to `PSTRAPS`<br />
* ACPI support (indicated by the PCI device ID changing to `0x0019`)<br />
* Notifiers to VRAM rather than just the main system RAM (check this)<br />
* Higher RAMDAC clock (260Mhz instead of 205)<br />
* Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)<br />
* AGP 2X bus support<br />
<br />
=== NV4 (RIVA TNT) ===<br />
<br />
<br />
* Hardware-accelerated stencil buffering <br />
<br />
=== NV5 (RIVA TNT2) ===<br />
<br />
==== NV5ULTRA (RIVA TNT2 Ultra) ====<br />
==== NV5VANTA (RIVA TNT2 Vanta; Vanta LT) ====<br />
==== NV6 (RIVA TNT2 M64) ====<br />
<br />
<br />
==Celsius architecture: Fixed function, T&L==<br />
<br />
==Kelvin architecture: Programmable shaders==<br />
<br />
==Rankine architecture==<br />
<br />
==Curie architecture==<br />
<br />
==Tesla architecture: GPGPU, unified shaders and CUDA ==<br />
<br />
==Tesla 2.0 architecture (GT2xx)==<br />
<br />
==Fermi architecture==<br />
<br />
==Kepler architecture==<br />
<br />
==Maxwell architecture==<br />
<br />
==Pascal architecture==<br />
<br />
==Volta architecture==<br />
<br />
==Turing architecture: Raytracing and ML==<br />
<br />
==Ampere architecture==<br />
<br />
==Lovelace / Hopper architecture==<br />
<br />
==Blackwell (GB1xx)==<br />
<br />
==Blackwell 2.0 (GB2xx)==<br />
<br />
==Rubin architecture (still in development)==<br />
This is Nvidia's 2026 architecture for GPUs.<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=List_of_GPUs&diff=1707List of GPUs2025-12-27T14:58:52Z<p>Starfrost: </p>
<hr />
<div>This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) sometimes made dozens of mdoels for a particular "series" and the list would be full of hundreds of almost identical SKUs.<br />
<br />
==Quadratic texture mappers==<br />
<br />
=== NV0 ===<br />
{{Main|NV0}}<br />
Not actually a GPU, but a series of VxD drivers under Windows 3.x to emulate the NV1 environment before it was ready. <br />
<br />
==== Features ====<br />
* Unknown<br />
<br />
=== NV1 ===<br />
{{Main|NV1}}<br />
<br />
The first GPU (or as it was dubbed by Nvidia at the time, "Multimedia Accelerator") designed by Nvidia and manufactured by SGS-Thomson Microelectronics (now STMicroelectronics), designed starting in 1993 and ending with its release in 1995. Its name is a contraction of "GX Next Version" (GXNV), as the GPU was designed by the same person, Curtis Priem, who designed the Sun GX for graphics workstations; Huang mandated the rename to NV1 for legal reasons. Unlike all later released Nvidia graphics cards, it does not render using triangles as the fundamental basis of graphical rendering but instead by using quad patching to implement quadratic texture mapped (QTM)'d curves. This has advantages for certain applications, such as computer-aided design and smooth curved surfaces, but is much more cumbersome for programming and game engine development, which was the intended market. There are also many other unique features, as Nvidia's strategy at this time was to attempt to monopolise all of the I/O on the graphical hardware. Ultimately it failed, due to its high cost, poor VGA functionality, and poor Direct3D (which was based on graphical hardware), and was discontinued in Q1 of 1996, not long after its launch. Apparently, at least 250,000 chips were sold, but most of them were returned without ever being put into cards due to poor sales; the poor sales also appear to have led to the cancellation of a 350 nm die shrink<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/090904.pdf (Microprocessor Report, July 10, 1995)</ref>.<br />
<br />
The original text (barring some minor redactions) of the "Strategic Collaboration Agreement" to develop the Nvidia NV1, RIVA 128 (NV3) and RIVA 128 ZX (NV3T) with SGS-Thomson can be found in a 1998 SEC filing, as it was an agreement that materially affected investors scoping out the company for potential investment during the IPO process<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref>.<br />
<br />
====Features====<br />
* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw<br />
* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support<br />
* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support<br />
* 3D Quadrilateral and Triangle rendering (however much slower than QTMs and not the primary focus)<br />
* Two-cache Gray-code indexed FIFO, [[PFIFO]] (one, <code>CACHE0</code>, with a size of one; another with 32 total entries) for graphical command ("object" submission)<br />
* Pseudo-C++ object system for total lunacy in design<br />
* Multi-channel DMA engine with 8 DMA channels, each with 8 subchannels (selectable by "context switching"), which can also be written to via PIO (<code>NV_USER</code>)<br />
* Oddly addressed [[RAMIN]] area for object submission<br />
* Hash table ([[RAMHT]]) for further object caching<br />
* Built-in error handling for invalid object submission via sending to [[RAMRO]]<br />
* Notification functionality via DMA into driver memory for GPU to driver communication<br />
* 1 to 4 MB of video memory, which can either be DRAM or VRAM<br />
* External RAMDAC (<code>NVDAC</code>), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU<br />
* Partially emulated VGA compatibility implemented via a separate PCI ID<br />
* Multiple clock sources (<code>VPLL</code> for pixel clock, varying based on resolution and color depth for controlling the CRT, and <code>MPLL</code> for everything else - the card ran at 100Mhz on average)<br />
<br />
This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card: <br />
* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)<br />
* Sega Saturn game port support (in the external DAC)<br />
* Partial VGA compatibility, largely emulated in software<br />
* EEPROM for storage of chip ID<br />
* [[NV1/DRM|Unused hardware-implemented encryption and digital rights management functionality]]<br />
* VESA Local Bus support, as well as PCI (seemingly only PCI versions were released as VLB was relatively short-lived)<br />
* Proprietary NVLIB API to avoid direct hardware programming <br />
<br />
=== NV2 ===<br />
{{Main|NV2}}<br />
The NV2 was a GPU designed under contract from Sega for the "Saturn V08", the first version of the project that became the Sega Dreamcast, starting in May 1995<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref> around the time of the announcement of the NV1. It was cancelled, at some point around early to mid 1996, due to internal pressure from Sega (especially their AM2 division) to move to a triangle-based model, combined with possible intransigence on Nvidia's part. SEGA still paid (loaned then forgave) NVIDIA 5 million dollars, which prevented the company from going bankrupt immediately. Most information on the technical implementation of the NV2 comes from Don Goddard, who was the main employee tasked with programming the NV2 (via a software emulator on the NV1) - which he described as "hella confusing", and with no debugging - at Sega of America.<br />
<br />
====New features====<br />
* Proto-shader microcode similar to the Nintendo 64 Reality Coprocessor & Reality Signal Processor GPU to handle texture compression, lighting, positions, and texture U/V coordinates<br />
* Possibly hardware-accelerated lighting <br />
* Color compression<br />
* Hardware-accelerated Z-buffering<br />
* Cartridge DMA (yes, cartridge) via the <code>PCART</code> subsystem<br />
* No VGA compatibility, as it was a game console GPU<br />
<br />
The status on if the NV2 ever worked as physical hardware is disputed; it was certainly taped out (even if only for one stepping, A0), and failed a demonstration to Sega, which may have triggered the cancellation of the project. However, some sources claim that a single engineer, Wayne Kogachi<ref>''The Nvidia Way'', Tae Kim, page 62</ref>, was assigned to and was successfully able to product a working chip. This was done in order to trigger an $1 million milestone payment, which was required due to the company's zero sales at the time. <br />
<br />
=== NV3 (Quadratic Texture Mapped version) ===<br />
{{Main|NV3 (QTM)}}<br />
<br />
Before [[David Kirk]] was hired at Nvidia, Nvidia were planning to launch a QTM-based "NV3" (entirely separate to the product launched as the Riva 128), a 100% functional superset of NV1 for PCs. It was announced around March 1996<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/100304.pdf (Microprocessor Report, March 5, 1996)</ref> for volume production in October of 1996, and was apparently going to be used in a home theater system by Lexicon, as the audio chip, provide an integrated RAMDAC and be generally much faster. It was most likely cancelled extremely quickly after its announcement, owing to Nvidia's new direction of developing triangle-based graphics accelerators. Very little else is known about it (other than the fact it would apparently be able to process 500,000 50-pixel triangles per second) and the original press release, published on 22 January 1996, does not mention the NV3, but also calls the NV1 NVIDIA's "first generation" product<ref>https://web.archive.org/web/19961112163232/http://www.nvidia.com/corporate/prlexicon.html ("LEXICON AND NVIDIA TEAM UP FOR NEXT GENERATION OF PC ENTERTAINMENT SOUND"; NVIDIA Corporation; 22 January 1996)</ref>. However, it does not seem to be a typo on the part of Microprocessor Report since it is repeated many times and explicitly stated to be a PC graphics card, which the NV2 was not.<br />
<br />
==Fixed function, no T&L (RIVA)==<br />
<br />
=== NV3 (RIVA 128)===<br />
{{Main|NV3}}<br />
[[David Kirk]] left Crystal Dynamics to replace [[Curtis Priem]] as the manager of GPU development at Nvidia after the NV2 was cancelled, and decided that sane design was the best way to go. Across nine months in 1996 and 1997, a triangle-based design was thrown together (completed in approximately January 1997?), tested extensively on a hardware simulator from another nearly-bankrupt company called [[Ikos]] (as Nvidia did not have the money for more than one revision of the chip without sales), and then taped out around 1 April 1997<ref>https://www.wave-report.com/1997%20Wave%20issues/wave707.html#707.4 (WAVE Report, 14 April 1997, "2 weeks out of fab")</ref>. The card was demoed at CGDC 1997, with Direct3D drivers that had only had crash bugs fixed hours before the demo and OpenGL drivers that had only achieved any functionality at all two days earlier<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/qAKzlj9qf5Q/m/lBQ25B1dhJMJ (USENET; "3D Chips at CGDC", Samuel S. Paik, 28 April 1997)</ref>, and were apparently "slow and buggy". The card launched as the "RIVA 128" ('''R'''eal-time '''I'''nteractive '''V'''ideo and '''A'''nimation accelerator, '''128'''-bit bus) in August 1997 (while the earliest known drivers are GDI-only NT 4.0 drivers compiled on 17 July 1997, these seem to have simply been an accidental release of pre-release drivers with an OEM card as they are an extreme outlier, with the earliest Win9x drivers and generic Nvidia drivers dated mid-August). OpenGL drivers were first released in alpha form in December 1997 and full form in March 1998. <br />
<br />
The card was very successful, at least compared to previous models and caused Nvidia's revenue to jump from $5.5 million in the first nine months of 1997 to $23.5 million in the last few months - several million were manufactured. Driver support ended in early 1999 (although 2D-only drivers continued to be compiled for Windows 2000 and XP until 2001) and manufacturing ended some time in mid to late 1999 for the ZX variant.<br />
<br />
====New features====<br />
* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)<br />
* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)<br />
* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)<br />
* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit<br />
* The ability to scale and stretch images while receiving them from system memory (`USCALED` and `USTRTCH` objects)<br />
* Generic image upload objects<br />
* AGP 1X bus support<br />
* DMA object submission for 3D<br />
* [[NV3 RMA|Real-Mode Access]], replacing [[NV1 RMC]]<br />
* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability<br />
* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)<br />
* Hardware-accelerated Z-buffering (in a released card)<br />
* Perspective-correct texture mapping (QTMs used forward texture mapping)<br />
* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded<br />
* Hardware-accelerated culling<br />
* Hardware-accelerated alpha buffer (for 3D acceleration)<br />
* Hardware-accelerated specular highlight<br />
* Hardware-accelerated texture offseting (varying the origin point of a texture)<br />
* Hardware fog support with 24-bit colour (vertex fog only)<br />
* Hardware-accelerated color space conversion <br />
* Hardware cursor now supports colour<br />
* YUV420 and YUV422 support<br />
* PC-98 support ("NEC mode")<br />
* Moved to a new 350 nm process rather than 500 nm<br />
* "Mediaport" on-card that allows plugging in external MPEG decoder<br />
* TV-Out support<br />
* RAMDAC and CRTC integrated on-die<br />
<br />
* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine<br />
* VGA and VESA compatibility, licensed from [[Weitek]]<br />
<br />
====Removed features====<br />
* Quadratic texture mapping (QTM) support<br />
* Quad patching more generally<br />
* [[NV1 DRM|Digital rights management]]<br />
* [[NV1 RMC]] (replaced with RMA)<br />
* Sound capability (Revision B and later)<br />
* Sega Saturn gamepad support<br />
* [[NV2]] microcode<br />
* VLB bus support<br />
* 3D capability at resolutions above 960*720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152*864<br />
<br />
=== NV3T (RIVA 128 ZX) ===<br />
{{Main|NV3#NV3T}}<br />
<br />
When Intel announced the Intel i740 GPU, Nvidia got cold feet and decided to rev a new version, revision C, of the RIVA 128, add some minor features, allow for 8 MB of VRAM and rebrand it as a new version.<br />
<br />
====Added features====<br />
* 8 MB of VRAM, rather than just 2 or 4<br />
* 1080p and 1920x1200 resolution support in the BIOS<br />
* PFIFO CACHE1 is now 64 slots deep instead of 32 <br />
* 3D capability at resolutions above 960*720 is better again<br />
* The ability to write to `PSTRAPS`<br />
* ACPI support (indicated by the PCI device ID changing to `0x0019`)<br />
* Notifiers to VRAM rather than just the main system RAM (check this)<br />
* Higher RAMDAC clock (260Mhz instead of 205)<br />
* Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)<br />
* AGP 2X bus support<br />
<br />
=== NV4 (RIVA TNT) ===<br />
<br />
<br />
* Hardware-accelerated stencil buffering <br />
<br />
=== NV5 (RIVA TNT2) ===<br />
<br />
==== NV5ULTRA (RIVA TNT2 Ultra) ====<br />
==== NV5VANTA (RIVA TNT2 Vanta; Vanta LT) ====<br />
==== NV6 (RIVA TNT2 M64) ====<br />
<br />
<br />
==Celsius architecture: Fixed function, T&L==<br />
<br />
==Kelvin architecture: Programmable shaders==<br />
<br />
==Rankine architecture==<br />
<br />
==Curie architecture==<br />
<br />
==Tesla architecture: GPGPU, unified shaders and CUDA ==<br />
<br />
==Tesla 2.0 architecture (GT2xx)==<br />
<br />
==Fermi architecture==<br />
<br />
==Kepler architecture==<br />
<br />
==Maxwell architecture==<br />
<br />
==Pascal architecture==<br />
<br />
==Volta architecture==<br />
<br />
==Turing architecture: Raytracing and ML==<br />
<br />
==Ampere architecture==<br />
<br />
==Lovelace / Hopper architecture==<br />
<br />
==Blackwell (GB1xx)==<br />
<br />
==Blackwell 2.0 (GB2xx)==<br />
<br />
==Rubin architecture (still in development)==<br />
This is Nvidia's 2026 architecture for GPUs.<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1706NVPlay2025-12-27T14:58:45Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| latest preview version = 1.0-rc3<br />
| latest preview date = {{Start date and age|2025|12|26|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]], [[wikipedia:Windows 3.x|Windows 3.x]] and [[wikipedia:Windows 9x|Windows 9x]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware; it can run in a Windows 9x DOSbox, and has also been tested on Windows 3.1 and even 3.0, so can be run at the same time as NVIDIA's drivers. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=Emulation_status&diff=1705Emulation status2025-12-27T14:57:52Z<p>Starfrost: </p>
<hr />
<div>This page details the emulation status for various NVIDIA GPUs.<br />
<br />
== NV3 ==<br />
Emulation is '''partially working'''. Most of the pipeline exists, the GPU is detected and drivers initialise on all known supported operating systems, and 2D partially works. The S2SB issue has been fixed, but buffer 0 is still not being set up correctly. Additionally, the DMA engine, required for 3D, is not yet emulated correctly (the format is understood but there are issues determining what to send).<br />
<br />
== NV4 ==<br />
Very early research and development is in progress. The Video BIOS first successfully ran in 86Box on 13 September 2025.</div>Starfrosthttps://nvwiki.org/index.php?title=List_of_GPUs&diff=1704List of GPUs2025-12-27T14:56:34Z<p>Starfrost: </p>
<hr />
<div>This is a list of all models of Nvidia GPUs. Although the focus of this wiki is on older models (approximately those released between 1995 and 2000), all GPUs manufactured by Nvidia are provided here for the purposes of reference. GPUs are sorted by ''architectural revision'', not branding, since Nvidia (especially in the 2000s) sometimes made dozens of mdoels for a particular "series" and the list would be full of hundreds of almost identical SKUs.<br />
<br />
==Quadratic texture mappers==<br />
<br />
=== NV0 ===<br />
{{Main|NV0}}<br />
Not actually a GPU, but a series of VxD drivers under Windows 3.x to emulate the NV1 environment before it was ready. <br />
<br />
==== Features ====<br />
* Unknown<br />
<br />
=== NV1 ===<br />
{{Main|NV1}}<br />
<br />
The first GPU (or as it was dubbed by Nvidia at the time, "Multimedia Accelerator") designed by Nvidia and manufactured by SGS-Thomson Microelectronics (now STMicroelectronics), designed starting in 1993 and ending with its release in 1995. Its name is a contraction of "GX Next Version" (GXNV), as the GPU was designed by the same person, Curtis Priem, who designed the Sun GX for graphics workstations; Huang mandated the rename to NV1 for legal reasons. Unlike all later released Nvidia graphics cards, it does not render using triangles as the fundamental basis of graphical rendering but instead by using quad patching to implement quadratic texture mapped (QTM)'d curves. This has advantages for certain applications, such as computer-aided design and smooth curved surfaces, but is much more cumbersome for programming and game engine development, which was the intended market. There are also many other unique features, as Nvidia's strategy at this time was to attempt to monopolise all of the I/O on the graphical hardware. Ultimately it failed, due to its high cost, poor VGA functionality, and poor Direct3D (which was based on graphical hardware), and was discontinued in Q1 of 1996, not long after its launch. Apparently, at least 250,000 chips were sold, but most of them were returned without ever being put into cards due to poor sales; the poor sales also appear to have led to the cancellation of a 350 nm die shrink<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/090904.pdf (Microprocessor Report, July 10, 1995)</ref>.<br />
<br />
The original text (barring some minor redactions) of the "Strategic Collaboration Agreement" to develop the Nvidia NV1, RIVA 128 (NV3) and RIVA 128 ZX (NV3T) with SGS-Thomson can be found in a 1998 SEC filing, as it was an agreement that materially affected investors scoping out the company for potential investment during the IPO process<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref>.<br />
<br />
====Features====<br />
* 2D acceleration supporting BitBlit (both src/dst and pattern), clipping rectangles, points, lines, lins (lines without their starting and ending pixels), hardware-accelerated monochrome cursors, and image upload (from various sources) with a maximum resolution of 1600x1200 and a maximum colour depth of 32-bit. Drivers implement GDI, possibly DCI (Windows 3.x drivers for the NV1 have not been identified) and DirectDraw<br />
* Hardware accelerated alpha-testing (chroma key), plane mask and clipping rectangle with double buffering and page flipping support<br />
* 3D quadratic texture mapping (QTM) for perfect curved surface rendering with bilinear filtering support<br />
* 3D Quadrilateral and Triangle rendering (however much slower than QTMs and not the primary focus)<br />
* Two-cache Gray-code indexed FIFO, [[PFIFO]] (one, <code>CACHE0</code>, with a size of one; another with 32 total entries) for graphical command ("object" submission)<br />
* Pseudo-C++ object system for total lunacy in design<br />
* Multi-channel DMA engine with 8 DMA channels, each with 8 subchannels (selectable by "context switching"), which can also be written to via PIO (<code>NV_USER</code>)<br />
* Oddly addressed [[RAMIN]] area for object submission<br />
* Hash table ([[RAMHT]]) for further object caching<br />
* Built-in error handling for invalid object submission via sending to [[RAMRO]]<br />
* Notification functionality via DMA into driver memory for GPU to driver communication<br />
* 1 to 4 MB of video memory, which can either be DRAM or VRAM<br />
* External RAMDAC (`NVDAC`), manufactured and, for some DACs, designed by SGS-Thomson (SGS-Thomson SGS-1732 and SGS-1764) for CRT control and image generation from the data sent to the GPU<br />
* Partially emulated VGA compatibility implemented via a separate PCI ID<br />
* Multiple clock sources (<code>VPLL` for pixel clock, varying based on resolution and color depth for controlling the CRT, and `MPLL` for everything else - the card ran at 100Mhz on average)<br />
<br />
This particular model of graphics card has many unique features that are not shared by any other model of Nvidia graphics card: <br />
* Non-Sound Blaster compatible sound card with MIDI playback on-die (in some models)<br />
* Sega Saturn game port support (in the external DAC)<br />
* Partial VGA compatibility, largely emulated in software<br />
* EEPROM for storage of chip ID<br />
* [[NV1/DRM|Unused hardware-implemented encryption and digital rights management functionality]]<br />
* VESA Local Bus support, as well as PCI (seemingly only PCI versions were released as VLB was relatively short-lived)<br />
* Proprietary NVLIB API to avoid direct hardware programming <br />
<br />
=== NV2 ===<br />
{{Main|NV2}}<br />
The NV2 was a GPU designed under contract from Sega for the "Saturn V08", the first version of the project that became the Sega Dreamcast, starting in May 1995<ref>https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-000618.txt (Nvidia Form S-1 for Registration of Securities, March 6, 1998)</ref> around the time of the announcement of the NV1. It was cancelled, at some point around early to mid 1996, due to internal pressure from Sega (especially their AM2 division) to move to a triangle-based model, combined with possible intransigence on Nvidia's part. SEGA still paid (loaned then forgave) NVIDIA 5 million dollars, which prevented the company from going bankrupt immediately. Most information on the technical implementation of the NV2 comes from Don Goddard, who was the main employee tasked with programming the NV2 (via a software emulator on the NV1) - which he described as "hella confusing", and with no debugging - at Sega of America.<br />
<br />
====New features====<br />
* Proto-shader microcode similar to the Nintendo 64 Reality Coprocessor & Reality Signal Processor GPU to handle texture compression, lighting, positions, and texture U/V coordinates<br />
* Possibly hardware-accelerated lighting <br />
* Color compression<br />
* Hardware-accelerated Z-buffering<br />
* Cartridge DMA (yes, cartridge) via the <code>PCART</code> subsystem<br />
* No VGA compatibility, as it was a game console GPU<br />
<br />
The status on if the NV2 ever worked as physical hardware is disputed; it was certainly taped out (even if only for one stepping, A0), and failed a demonstration to Sega, which may have triggered the cancellation of the project. However, some sources claim that a single engineer, Wayne Kogachi<ref>''The Nvidia Way'', Tae Kim, page 62</ref>, was assigned to and was successfully able to product a working chip. This was done in order to trigger an $1 million milestone payment, which was required due to the company's zero sales at the time. <br />
<br />
=== NV3 (Quadratic Texture Mapped version) ===<br />
{{Main|NV3 (QTM)}}<br />
<br />
Before [[David Kirk]] was hired at Nvidia, Nvidia were planning to launch a QTM-based "NV3" (entirely separate to the product launched as the Riva 128), a 100% functional superset of NV1 for PCs. It was announced around March 1996<ref>https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/100304.pdf (Microprocessor Report, March 5, 1996)</ref> for volume production in October of 1996, and was apparently going to be used in a home theater system by Lexicon, as the audio chip, provide an integrated RAMDAC and be generally much faster. It was most likely cancelled extremely quickly after its announcement, owing to Nvidia's new direction of developing triangle-based graphics accelerators. Very little else is known about it (other than the fact it would apparently be able to process 500,000 50-pixel triangles per second) and the original press release, published on 22 January 1996, does not mention the NV3, but also calls the NV1 NVIDIA's "first generation" product<ref>https://web.archive.org/web/19961112163232/http://www.nvidia.com/corporate/prlexicon.html ("LEXICON AND NVIDIA TEAM UP FOR NEXT GENERATION OF PC ENTERTAINMENT SOUND"; NVIDIA Corporation; 22 January 1996)</ref>. However, it does not seem to be a typo on the part of Microprocessor Report since it is repeated many times and explicitly stated to be a PC graphics card, which the NV2 was not.<br />
<br />
==Fixed function, no T&L (RIVA)==<br />
<br />
=== NV3 (RIVA 128)===<br />
{{Main|NV3}}<br />
[[David Kirk]] left Crystal Dynamics to replace [[Curtis Priem]] as the manager of GPU development at Nvidia after the NV2 was cancelled, and decided that sane design was the best way to go. Across nine months in 1996 and 1997, a triangle-based design was thrown together (completed in approximately January 1997?), tested extensively on a hardware simulator from another nearly-bankrupt company called [[Ikos]] (as Nvidia did not have the money for more than one revision of the chip without sales), and then taped out around 1 April 1997<ref>https://www.wave-report.com/1997%20Wave%20issues/wave707.html#707.4 (WAVE Report, 14 April 1997, "2 weeks out of fab")</ref>. The card was demoed at CGDC 1997, with Direct3D drivers that had only had crash bugs fixed hours before the demo and OpenGL drivers that had only achieved any functionality at all two days earlier<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/qAKzlj9qf5Q/m/lBQ25B1dhJMJ (USENET; "3D Chips at CGDC", Samuel S. Paik, 28 April 1997)</ref>, and were apparently "slow and buggy". The card launched as the "RIVA 128" ('''R'''eal-time '''I'''nteractive '''V'''ideo and '''A'''nimation accelerator, '''128'''-bit bus) in August 1997 (while the earliest known drivers are GDI-only NT 4.0 drivers compiled on 17 July 1997, these seem to have simply been an accidental release of pre-release drivers with an OEM card as they are an extreme outlier, with the earliest Win9x drivers and generic Nvidia drivers dated mid-August). OpenGL drivers were first released in alpha form in December 1997 and full form in March 1998. <br />
<br />
The card was very successful, at least compared to previous models and caused Nvidia's revenue to jump from $5.5 million in the first nine months of 1997 to $23.5 million in the last few months - several million were manufactured. Driver support ended in early 1999 (although 2D-only drivers continued to be compiled for Windows 2000 and XP until 2001) and manufacturing ended some time in mid to late 1999 for the ZX variant.<br />
<br />
====New features====<br />
* Triangle-based rendering mostly compliant with the DirectX 5.0 specification (apparently, they did not receive the final spec in time, resulting in certain blending modes being missing)<br />
* Non-crappy Direct3D drivers (the NV1 D3D drivers are simply wrappers around the GPU's native quad patching)<br />
* Full OpenGL Installable Client Driver with OpenGL 1.1 compliance (released in early 1998)<br />
* GDI acceleration for clipped rectangles, transparent bitmaps, and 1bpp color-expanded bit blit<br />
* The ability to scale and stretch images while receiving them from system memory (`USCALED` and `USTRTCH` objects)<br />
* Generic image upload objects<br />
* AGP 1X bus support<br />
* DMA object submission for 3D<br />
* [[NV3 RMA|Real-Mode Access]], replacing [[NV1 RMC]]<br />
* Up to 4 buffers which can be moved around in memory and have their pitch and color format changed at any time, the 4th buffer is hardcoded in the drivers to be used as a "zeta buffer" (currently a Z buffer, later stencil buffering was added), allowing much more versatile (and annoying) screen-to-screen blit capability<br />
* Multiple interpolation modes for texture interpolation (zero order hold, "Microsoft" zero order hold and full order hold)<br />
* Hardware-accelerated Z-buffering (in a released card)<br />
* Perspective-correct texture mapping (QTMs used forward texture mapping)<br />
* RGB565 textures (later drivers only); technically, the output format in 3D is always 32-bit, but only 16-bit source texture data can be loaded<br />
* Hardware-accelerated culling<br />
* Hardware-accelerated alpha buffer (for 3D acceleration)<br />
* Hardware-accelerated specular highlight<br />
* Hardware-accelerated texture offseting (varying the origin point of a texture)<br />
* Hardware fog support with 24-bit colour (vertex fog only)<br />
* Hardware-accelerated color space conversion <br />
* Hardware cursor now supports colour<br />
* YUV420 and YUV422 support<br />
* PC-98 support ("NEC mode")<br />
* Moved to a new 350 nm process rather than 500 nm<br />
* "Mediaport" on-card that allows plugging in external MPEG decoder<br />
* TV-Out support<br />
* RAMDAC and CRTC integrated on-die<br />
<br />
* "DFB" (Dumb Framebuffer) in PCI BAR1 allowing you to write into the GPU directly without interfacing with the 2D or 3D acceleration engine<br />
* VGA and VESA compatibility, licensed from [[Weitek]]<br />
<br />
====Removed features====<br />
* Quadratic texture mapping (QTM) support<br />
* Quad patching more generally<br />
* [[NV1 DRM|Digital rights management]]<br />
* [[NV1 RMC]] (replaced with RMA)<br />
* Sound capability (Revision B and later)<br />
* Sega Saturn gamepad support<br />
* [[NV2]] microcode<br />
* VLB bus support<br />
* 3D capability at resolutions above 960*720 due to the GPU keeping more data in VRAM, NV1 could do up to 1152*864<br />
<br />
=== NV3T (RIVA 128 ZX) ===<br />
{{Main|NV3#NV3T}}<br />
<br />
When Intel announced the Intel i740 GPU, Nvidia got cold feet and decided to rev a new version, revision C, of the RIVA 128, add some minor features, allow for 8 MB of VRAM and rebrand it as a new version.<br />
<br />
====Added features====<br />
* 8 MB of VRAM, rather than just 2 or 4<br />
* 1080p and 1920x1200 resolution support in the BIOS<br />
* PFIFO CACHE1 is now 64 slots deep instead of 32 <br />
* 3D capability at resolutions above 960*720 is better again<br />
* The ability to write to `PSTRAPS`<br />
* ACPI support (indicated by the PCI device ID changing to `0x0019`)<br />
* Notifiers to VRAM rather than just the main system RAM (check this)<br />
* Higher RAMDAC clock (260Mhz instead of 205)<br />
* Much higher colour depths in 2D due to the higher amount of VRAM and higher maximum pixel clock (16-bit is still only supported in 3D, because only 16-bit texture formats can be loaded by PGRAPH)<br />
* AGP 2X bus support<br />
<br />
=== NV4 (RIVA TNT) ===<br />
* Hardware-accelerated stencil buffering <br />
<br />
=== NV5 (RIVA TNT2) ===<br />
<br />
==== NV5ULTRA (RIVA TNT2 Ultra) ====<br />
==== NV5VANTA (RIVA TNT2 Vanta; Vanta LT) ====<br />
==== NV6 (RIVA TNT2 M64) ====<br />
<br />
<br />
==Celsius architecture: Fixed function, T&L==<br />
<br />
==Kelvin architecture: Programmable shaders==<br />
<br />
==Rankine architecture==<br />
<br />
==Curie architecture==<br />
<br />
==Tesla architecture: GPGPU, unified shaders and CUDA ==<br />
<br />
==Tesla 2.0 architecture (GT2xx)==<br />
<br />
==Fermi architecture==<br />
<br />
==Kepler architecture==<br />
<br />
==Maxwell architecture==<br />
<br />
==Pascal architecture==<br />
<br />
==Volta architecture==<br />
<br />
==Turing architecture: Raytracing and ML==<br />
<br />
==Ampere architecture==<br />
<br />
==Lovelace / Hopper architecture==<br />
<br />
==Blackwell (GB1xx)==<br />
<br />
==Blackwell 2.0 (GB2xx)==<br />
<br />
==Rubin architecture (still in development)==<br />
This is Nvidia's 2026 architecture for GPUs.<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=File:Nvplay_unsupported.png&diff=1702File:Nvplay unsupported.png2025-12-27T01:21:46Z<p>Starfrost: NVplay showing its unsupported screen in VGA mode Windows 2000. Windows NT is not compatible with NVPlay as NTVDM does not allow direct hardware access for good reasons.</p>
<hr />
<div>== Summary ==<br />
NVplay showing its unsupported screen in VGA mode Windows 2000. Windows NT is not compatible with NVPlay as NTVDM does not allow direct hardware access for good reasons.</div>Starfrosthttps://nvwiki.org/index.php?title=Timeline&diff=1699Timeline2025-12-26T23:06:10Z<p>Starfrost: </p>
<hr />
<div>This is a timeline of the early history of Nvidia.<br />
<br />
== 1950s and earlier ==<br />
* 1948: David S. H. Rosenthal (one of the NV1 designers) is born.<br />
* March 6, 1950: John Nickolls is born.<br />
* 1958 or 1959: [[Curtis Priem]] is born. For some reason, his exact birth year is not known.<br />
* May 2, 1959: Chris Malachowsky is born.<br />
* 1959: The revolutionary Sketchpad program is created on the MIT TX-2 computer by a team led by Ivan Sutherland (later of Evans and Sutherland). It allowed the drawing of objects using a light pen and was one of the first entirely graphical programs and a pioneer of human-computer interaction as a concept.<br />
<br />
== 1960s ==<br />
* 1960: David Kirk (Nvidia's chief scientist from 1997 until 2009) is born.<br />
* February 17, 1962: Jensen Huang is born in Taiwan.<br />
* 1958-1962: The "perceptron" concept (the predecessor to modern artificial neural networks) is first explored by Frank Rosenblatt.<br />
* 1964: The first 3D computer art is created, a three-dimensional hand.<br />
* 1967: Jensen Huang's family moves to Thailand.<br />
* 1969: Evans and Sutherland, Inc. releases the LDS-1 (Line Drawing System-1), the first commercial 3D graphics system.<br />
* 1969: An extremely influential book on perceptrons by AI researchers Marvin Minsky and Seymour Papert causes serious damage to the reputation of the perceptron concept and ends serious research into them for the next twenty years. This is despite the book acknowleging the strengths and setting out to be an overall evaluation of perceptrons rather than a debunking of their efficacy; this may be due to the small size and generally close-knit AI community of the time. However, even if this book had never been published, neural networks capable of serious learning ability were not plausible even on supercomputers until the 1990s, due to the very high resource use of these programs; nevertheless, it does not prevent the invention of backpropagation by a Finnish master's student in 1970.<br />
* 1969: The Special Interest Group in Computer Graphics and Interactive Techniques (SIGGRAPH) is founded by the ACM (Association for Computing Machinery). It becomes one of the most prominent conferences for discussion of, and research into, computer graphics as a field.<br />
<br />
== 1970s ==<br />
* 1973: Jensen Huang is sent to the United States by his parents. They believed they were sending him to a prestigious private school, but they actually sent him to the Oneida Baptist Institute, a reform school for troubled children in Kentucky<br />
* 1975: Huang's family move to the United States and he relocates to Oregon to live with them.<br />
* 1977: Approximate birth date of Ian Buck (one of the inventors of GPGPU) based on his university records.<br />
* 1978: Jensen Huang gets a job at Denny's as a dishwasher, eventually promoted to a busboy and then a waiter, to supplant his income while he studies at university. This era of his life later becomes a large part of his mythology, and the Denny's restaurants of Silicon Valley became a general hangout spot in later years. He was also apparently a nationally ranked table tennis player during this time.<br />
<br />
== 1980s ==<br />
* 1980: As a part of a research project led by ex-E&S employee Jim Clark. the first integrated circuit specifically intended for 3D geometry processing is created, the Geometry Engine.<br />
* 1980: Jensen Huang starts a course in electrical engineering at Oregon State University.<br />
* August 12, 1981: IBM announces its Personal Computer, using an Intel CPU and Microsoft-supplied (via Seattle Computer Products) operating system. This is the start of the modern PC "Wintel" standard architecture and the products that Nvidia's add-on boards would be available for.<br />
* 1981: [[Weitek]], designer of the Nvidia VGA cores, is founded, initially to develop floating-point units and other accelerator chips.<br />
* 1982: SiliconGraphics Computer Systems, Inc. is founded. <br />
* 1982: Microsoft starts working on an implementation of the obscure Graphical Kernel System (GKS) standard for device-independent graphics called GDI (Graphics Device Interface.)<br />
* 1982: Possibly after seeing a demonstration of the "Visi On" preemptive OS for the PC, Microsoft merges the GDI with another project, Interface Manager, a standard interface library for Microsoft's apps division, to create the "Microsoft Window Manager" project, later renamed Microsoft Desktop and then simply to Windows. The project slowly becomes an almost complete operating system (except for disk I/O and filesystem services, which are still provided by MS-DOS).<br />
* 1982: Priem is hired at a company called Vermont Microsystems, Inc. to develop graphics hardware in collaboration with IBM.<ref>The Nvidia Way (Kae, Tim; 2024), pp. 25. ISBN 9781324086710).</ref><br />
* 1982: SGS-Thomson Microelectronics is founded from the merger of the French state-owned semiconductor company SGS and the Italian Thomson Microelectronics.<br />
* 1984: The approximate birth date of Mark Harris (founder of GPGPU.org), based on his university records.<br />
* Early-Mid 1980s: Chris Malachowsky is hired at HP to work on the HP 1000 line of computers while finishing his master's degree from Santa Clara University.<br />
* 1984: Jensen Huang graduates alongside his future wife Lori Mills. He interviews at Texas Instruments, AMD and LSI Logic; he receives offers from the latter two and elects to join AMD as an engineer. <br />
* 1984: The "IRIS 1000" terminal and workstation line is released by SGI at a mid-five figure cost; it is one of the most powerful graphics workstations of its era and the start of SGI's rise to cultural prominence.<br />
* August 14, 1984: IBM announces its third-generation (or second depending on how the XT gets counted) PC - the Advanced Technology (PC/AT). One of the graphics options is the Professional Graphics Controller, a CGA-compatible three-board coprocessor with an 8Mhz 8088 that can do up to 640x480 at an 8bpp bit depth (256 colours), and provides a ROM to perform 2D and 3D graphics calculations via both assembly and a human-readable command set, including very advanced font rendering for the time. This was designed by Vermont Microsystems; Curtis Priem's name is included in the ROM, alongside two other programmers, one of whom now works at NVIDIA.<br />
* 1984: Priem leaves Vermont Microsystems and moves to a company called GenRad, one of the largest manufacturers of electronic testing equipment at the time; however, unbeknowst to Priem, the company is in financial distress and suffering from poor management.<br />
* December 1984: Jensen Huang and Lori Mills (a day after his proposal to her) almost die in a car crash in the Oregon mountains. He twisted his neck, requiring stitches and a neck brace.<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 26. ISBN 9780593832691</ref><br />
* 1985: One of Huang's coworkers convinces him to leave AMD and work for LSI Logic, then one of the most cutting-edge silicon design and fabrication companies, instead.<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 29. ISBN 9780593832691</ref>. He is later assigned to the Sun Microsystems account, where he meets Priem and Malachowsky.<ref>The Nvidia Way (Kae, Tim; 2024), pp. 22. ISBN 9781324086710).</ref><br />
* 1985: Lori Mills is hired at SGI.<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 30. ISBN 9780593832691</ref><br />
* 1986: Pixar is founded; its first serious work, the "Luxo Jr." animated spot, shown at SIGGRAPH in 1986, is one of the first 3D animated short films to be considered credible by the animation industry.<br />
* 1986: The Texas Instruments Graphics Architecture (TIGA) line of 2D GPUs is released for the PC; it is one of the earliest attempts at proper PC graphics but fails due to the lack of a standardised operating system to write drivers for.<br />
* 1986: Priem leaves GenRad and, due to his reputation as the designer of the IBM PGC, is shortly after hired at Sun Microsystems, to work on their next-generation graphics architecture alongside Chris Malachowsky.<br />
* ~1986: Vermont Microsystems releases the IM-1024, the successor to the PGC. It swaps out the 8Mhz 8088 for a 10Mhz 80186 (much faster due to much more efficient operation) and allows up to 1024x768x8bpp rendering; this was delivered via a Windows 1.03 driver. It does not appear Priem was involved, as he left around the time of the completion of the PGC.<br />
* 1986-1987: Chris Malachowsky is hired by Sun after finishing his master's degree, after considering both moving to the UK division of HP in Bristol and various other US-based tech companies, including Evans and Sutherland.<br />
* October 1987: IBM releases the catchily named 8514/A, the first fixed-function PC graphics accelerator. It is later copied by many companies including ATi and S3 Graphics, becoming the basis of many early 1990s PC graphics accelerators.<br />
* January 21, 1988: Curtis Priem produces several documents about the "CG6" architecture, which later became his second graphics card design, the Sun GX.<ref>''Sun GX TEC Reference'' (Priem, Curtis; 21 January 1988) http://www.bitsavers.org/components/lsiLogic/sparc/GX/Sun_GX_TEC_Jan1988.pdf)</ref> <ref>''Sun GX FBC Reference'' (Priem, Curtis; 21 January 1988) http://www.bitsavers.org/components/lsiLogic/sparc/GX/Sun_GX_FBC_Jan1988.pdf</ref><br />
* 1988: Programmer's Hierarchical Interactive Graphics System (PHIGS), an early 3D graphics standard, is released; it is adopted by many companies.<br />
* 1988: Namco releases the System 21 "Polygonizer", the first 3D-capable arcade board, and the flat-shaded 3D game "Winning Run"; possibly the first time the average gamer could obtain access to reasonably fast 3D graphics. <br />
* 1989: The Sun GX (possibly codenamed "CG6"), a primarily quadliateral based 2D/3D graphics card, is released as an option for Sun's line of workstations, designed by Priem. Priem and another Sun employee, Bruce Factor, releases a flight simulator, Aviator, for GX-based Sun workstations and continue to release updates for the next few years, eventually commercialising the program. Later on, Sun bundled the GX with various Sun-3 and SPARCstation workstations<ref>https://old.hotchips.org/wp-content/uploads/hc_archives/hc01/3_Tue/HC1.S8/HC1.8.2.pdf</ref>. The manufacturing was handled by LSI Logic and hense Jensen Huang, as he was the person in charge of the Sun account.<ref>The Nvidia Way (Kae, Tim; 2024), pp. 32. ISBN 9781324086710).</ref>. A PHIGS implementation is provided.<br />
<br />
== 1990-1992 ==<br />
* 1990: SGI releases the IrisVision, a 3D GPU for the PC capable of flat and Gouraud shading. Only around 5,000 units are sold due to the exorbitantly high cost, and SGI eventually spins off the team responsible for it into another company called Pellucid.<br />
* ~1990: After the success of the GX project, Huang is allowed by the founder and CEO of LSI Logic, Wolf Corrigan, to create a division that would sell SoCs combining multiple funcitons onto one chip.<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 33. ISBN 9780593832691</ref><br />
* 1991: Lori Mills leaves SGI to raise her and Jensen's two children. This seriously stretches their personal finances despite Jensen holding a secure and well paying job. Malachowsky's wife did a similar thing; later, Malachowsky conceded that both him and Huang's wives were "superior engineers" to them.<br />
* Early 1990s: Due to the massively accelerating pace and performance of PCs, running texture mapped 3D games with a reasonable level of quality becomes an increasingly plausible and cheap option. By 1997, over 70 companies are founded to attempt to exploit this market. One of these attempts is made by Malachowsky and Priem, who proposed to Sun that they enter into the gaming graphics business - the proposal is rejected.<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 35. ISBN 9780593832691</ref>. <ref>The Nvidia Way (Kae, Tim; 2024), pp. 22. ISBN 9781324086710).</ref>. Apparently, the dysfunctional work environment of Sun got so bad that he would regularly start crying in the various recreation areas of Sun's campus<ref>The Nvidia Way (Kae, Tim; 2024), pp. 37. ISBN 9781324086710).</ref><br />
* 1992: SGI cleans up and renames IRIS GL (its graphics library) to OpenGL, turning it over to the OpenGL Architecture Review Board (ARB; later handed to Khronos Group in 2006) and releasing it as an open graphics API standard.<br />
* Late 1992: After the failure of both their proposal to Sun and and a similar proposal to SGI to enter the PC consumer 3D graphics space, Malachowsky and Priem contact Huang to discuss the concept of founding a 3D graphics company; one version of this proposal, before Huang was involved, involved building a chip for the Korean ''chaebol'' Samsung. After he got involved in the project, Huang was assigned as the CEO of this hypothetical company due to his larger amount of business experience; additionally, the trio's coworkers at Sun were skeptical of Malachowsky and Priem's ability to work together. This may have been a wise observation, considering they often broke out into screaming matches against each other. After some time and many meetings in various seedy Denny's restaurants, Jensen accepts after determining that it was possible to make at least $50 million of revenue from the venture<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 41. ISBN 9780593832691</ref>.<br />
* December 31, 1992: Curtis Priem resigns from Sun Microsystems to jumpstart the new venture (the families of Malachowsky and Huang were demanding that they wait until the other resigned). Several Sun employees follow him despite the high risk and lack of any funding due to his reputation as the founder of the GX.<ref>The Nvidia Way (Kae, Tim; 2024), pp. 40. ISBN 9781324086710).</ref><br />
<br />
== NV1 era: 1993-1995 ==<br />
* Early 1993: The founders of Nvidia stop going to the Denny's where they were discussing the founding of Nvidia due to an outbreak of gang warfare near the restaurant leading to the windows being shot through.<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 41. ISBN 9780593832691</ref>. Later on, a plaque was inserted to commemorate the founding of Nvidia allegedly occurring within it, although in reality it was simply discussed there and formally founded inside Priem's townhouse.<br />
* February 17, 1993: Jensen Huang resigns from LSI Logic after spending six weeks transferring his projects to other managers within the company.<ref>The Nvidia Way (Kae, Tim; 2024), pp. 42. ISBN 9781324086710).</ref><br />
* Early March 1993: Chris Malachowsky, after an attempt by his manager to convince him to move to work on the project that later became Java fails, resigns from Sun to join Nvidia. His manager let them take and upgrade their personal workstations at Sun for Nvidia's use.<br />
* April 5, 1993: NVidia, Inc. is formally founded in Curtis Priem's townhouse with a $200 initial capitalisation. The equity is initially split equally between the three founders. The name is a pun on "New Venture" and also the "GX next version" project that Priem and Malachowsky initially proposed to Sun; Huang forced them to rename it to NV1 to prevent any possible copyright issues with their former employers. The first headquarters of the company were two of the three bedrooms of Priem's house; an impromptu bedroom was set up in the garage.<ref>The Thinking Machine (Witt, Stephen; 2025), pp. 43. ISBN 9780593832691</ref>. Early employees included David Rosenthal (who had mvoed to the US from Britain at this point).<br />
* April 8, 1993: Curtis Priem changes the description of his SPARCstation 1 UUCP server to read "Nvidia"<ref>UUCP Mapping Project: https://groups.google.com/g/comp.mail.maps/c/QmEyGC73D_c/m/34dhQKz4ZOYJ</ref><br />
* Mid 1993: Nvidia, despite a bad pitch involving a commodity PC being hacked to use a Sun GX, receives $4 million in seed funding from Sutter Hill Ventures and Sequoia Capital, mostly due to the founders' reputation. Shortly after this, the company rented office space in Sunnyvale, California. <ref>The Nvidia Way (Kae, Tim; 2024), pp. 53. ISBN 9781324086710).</ref><br />
* June 29, 1993: Nvidia refiles its articles of incorporation to allow the issuance of "Series A" stock shares to third parties other than the founders. This is most likely an approximate date to when Sutter Hill and Sequoia invested.<br />
* October 20, 1993: Version 1.0 of the "NV Architecture Specification" document is produced; it is an overview of the architecture of the graphics accelerators that Nvidia intends to build.<ref>SGS-Thomson/Nvidia Strategic Collaboration Agreement (SEC filing), including 1996 and 1998 amendments. Available online at https://contracts.onecle.com/nvidia/sgs.collab.1993.11.10.shtml)</ref> <br />
* November 1993: Pellucid is taken over by another company called Media Vision to develop sound cards and 2D/3D graphics products.<br />
* November 10, 1993: Nvidia signs an agreement with SGS-Thomson Microelectronics to develop a graphics accelerator which will be fabricated by SGS and jointly marketed by Nvidia and SGS.<ref>SGS-Thomson/Nvidia Strategic Collaboration Agreement (SEC filing), including 1996 and 1998 amendments. Available online at https://contracts.onecle.com/nvidia/sgs.collab.1993.11.10.shtml)</ref>. The chip will be branded NV1 and split into two variants; a mid-range 64-bit bus DRAM variant ("NV1-D64") and a high-end 32-bit bus variant using VRAM memory ("NV1-V32"). SGS paid Nvidia $500,000 in return for the rights to market the D64 variant only and brand it as the STG-2000; SGS also provided the RAMDAC and legacy VGA support for the NV1 (becoming the STG-1732/1764 chips) and deployed certain engineers to assist Nvidia with the NV1. <br />
* November 19, 1993: According to code comments, development of the NVidia Hardware Simulator (NV0) and a dummy Resource Manager to simulate an Nvidia device under Windows 3.1 had started by this time.<br />
* December 10, 1993: id Software releases DOOM. While technically not a 3D game, the BSP rendering method used removed almost all limitations of 2D and the game completed the popularisation of both 3D games and the first-person shooter genre. It also had a role in the early development of mods, the speedrunning community and online gaming.<br />
* Early 1994: Several Media Vision employees, many of which had been around since the days of the IrisVision at SGI, leave out of frustration at the company's seeming unwillingness to pursue 3D graphics and create 3D/fx Interactive, Inc. (later shortened to 3Dfx) Initially it intended to build a motherboard but its funder, Gordon Campbell, requested an add-on card to be produced as well as arcade machines; the company was incorporated on February 24, 1994. <br />
* May 17, 1994: The CEO of Media Vision, Paul Jain resigns due to the exposure of massive amounts of financial fraud by the company. The company enters into bankruptcy proceedings, shuts down its graphics business and is reorganised as Aureal Semiconductor. Jain is indicted, but never convicted, of 27 counts of various fraud charges by the US Department of Justice, although both him and the CFO of the company are eventually fined.<br />
* Mid-1994: An initial version of the NV1 design is completed and revision A01 of the NV1 is taped out and sent to ST. A VHS tape exists of the chips being returned to Nvidia, but it is not available. Nvidia was paid $1 million for the milestone under the terms of the Strategic Collaboration Agreement.<ref>SGS-Thomson/Nvidia Strategic Collaboration Agreement (SEC filing), including 1996 and 1998 amendments. Available online at https://contracts.onecle.com/nvidia/sgs.collab.1993.11.10.shtml)</ref> <br />
* June 15, 1994: Driver development for a real [[Software#Resource Manager]] running, presumably, under a real NV1 chip, had started by this time. <br />
* July 26, 1994: Nvidia reports some details of their architecture to the Jon Peddle Report, who had advised Huang not to found Nvidia.<ref>Nvidia's Quadratic Processor: The NV1 (available online at https://www.computer.org/publications/tech-news/chasing-pixels/nvidias-quadratic-processor-the-nv1)</ref>. The company is also mentioned in the 25 July 1994 issue of InfoWorld.<br />
* August 1, 1994: Under the terms of the Strategic Collaboration Agreement, Nvidia was paid another $500,000 by SGS-Thomson.<ref>SGS-Thomson/Nvidia Strategic Collaboration Agreement (SEC filing), including 1996 and 1998 amendments. Available online at https://contracts.onecle.com/nvidia/sgs.collab.1993.11.10.shtml)</ref> <br />
* November 1, 1994: Another $500,000 payment to Nvidia was made.<ref>SGS-Thomson/Nvidia Strategic Collaboration Agreement (SEC filing), including 1996 and 1998 amendments. Available online at https://contracts.onecle.com/nvidia/sgs.collab.1993.11.10.shtml)</ref> <br />
* ~Late 1994: Revision A02 of the NV1, presumably fixing bugs with earlier revisions, is taped out.<br />
* December 14, 1994: Nvidia again amends its articles of incorporation to allow Series B venture capitalists to receive shares. This is most likely indicative of an approximate date for Nvidia's Series B financing.<br />
* December 24, 1994: Despite their public support for OpenGL, a skunkworks team within Microsoft starts development of Microsoft's proprietary standard graphical API for Windows, DirectX (initially called the "Windows 95 Game SDK"). Initially, only the 2D DirectDraw component was released, but a 3D API was released in early 1996 with version 2.0. This API is based on traditional triangle-based rendering with perspective-correct texture mapping, and the rapid standardisation of game develoeprs on this API, due to Microsoft's near-monopoly on the market, will cause Nvidia serious problems in the future.<br />
* January 4, 1995: An Nvidia employee helps a Usenet user find Video for Windows 1.1d and the Indeo 3.2 codec<ref>"Info Request"; USENET comp.graphics; https://groups.google.com/g/comp.graphics/c/MZcpuy751l8/m/5fHqF3jUJUEJ</ref><br />
* January 11, 1995: An Nvidia employee inquires about printing off a large number of CD-Rs ("initially 20, then 100, then a large number"). Possibly this means that the NV1 SDK was first released shortly after this time.<ref>"RECORDABLE CD--R advice sought; S.Page; USENET alt.cdrom; https://groups.google.com/g/comp.graphics/c/MZcpuy751l8/m/5fHqF3jUJUEJ)</ref><br />
* January 16, 1995: By this point, some kind of website existed at https://nvidia.com.<br />
* January-April 1995: An Nvidia employee posts many times about use of the FrameMaker software for writing program help on USENET; presumably documentation of the NV1 was already progressing at this stage.<br />
* March 7, 1995: The "QUADTEX" SDK demo, demonstrating the utilisation of quadratic texture mapping to warp a 3D object, has started development by this time.<br />
* May 23, 1995: The NV1 is officially announced via a press release on Nvidia's website and various SGS-Thomson marketing activities. The reaction appears to have been rather muted, with a few trade press articles published at the time and a rather enthusiastic declaration that the NV1 was the "NEXT GENERATION OF PC GAME PROGRAMMING" on USENET.<br />
* May 1995: The [[NV2]] project is started by Nvidia and Sega.<ref>NVIDIA Notes to Financial Statements; SEC Form S1/A; available online at https://www.sec.gov/Archives/edgar/data/1045810/0001012870-98-001519.txt</ref><br />
* June 1995: By this point, revision B01 of the NV1, including performance improvements for bilinear filtering, the [[NV1 DRM]] engine and various errata fixes, has been produced.<br />
* June 15, 1995: Version 0.4 of the "Programming NV" document is produced. Nvidia amends its articles of incorporation to allow Series C venture capitalists to receive shares. This is most likely indicative of an approximate date for Nvidia's Series C financing.<br />
* August 21, 1995: By this time Nvidia has created an adapter board that allows Sun Microsystems SBUS expansion boards to be inserted into slots intended for the VESA Local Bus used on some early 1990s (typically 486-based) computers; refer to [[SBus to VL Converter]] for further information. <br />
* August 24, 1995: Windows 95 is released; Nvidia has already been working on porting their drivers to it for several months. <br />
* November 23, 1995: The NV1 is released.<br />
== Notes ==<br />
== References ==</div>Starfrosthttps://nvwiki.org/index.php?title=SBus_to_VL_Converter&diff=1698SBus to VL Converter2025-12-26T23:05:33Z<p>Starfrost: references</p>
<hr />
<div>The '''SBus to VL Converter''' may have been NVIDIA's first product released for sale, available by August 1995<ref>https://discmaster.textfiles.com/view/16967/CDware_Sep-Dec_1995.bin/.products/.wais/wais-src/Hardware_Peripherals/Interface_Devices_and_Controllers/SBUS-to-VL_Converter.html</ref>. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the [[NV1]] (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been sold by phone order or via some other non-retail channel; the product was probably intended for use on Sun Solaris. The fact that it was listed in a catalog implies it was intended to be sold or at least showcased.<br />
<br />
Later on (by March 1996<ref>https://discmaster.textfiles.com/view/20246/Catalyst%20CDWARE%201996%20May%20to%20August.iso/.products/.wais/wais-src/Hardware_Peripherals/Interface_Devices_and_Controllers/SBUS-to-VL_Converter.html</ref>), the registered address was changed (from 1206 E. Arques Avenue, the site of Nvidia's first offices, to 1226 Tiros Way, its second offices) and a fax address added for someone called "Chris". This presuambly means that it was still being sold at some level by that time.</div>Starfrosthttps://nvwiki.org/index.php?title=SBus_to_VL_Converter&diff=1697SBus to VL Converter2025-12-26T23:04:29Z<p>Starfrost: </p>
<hr />
<div>The '''SBus to VL Converter''' may have been NVIDIA's first product released for sale, available by August 1995. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the [[NV1]] (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been sold by phone order or via some other non-retail channel; the product was probably intended for use on Sun Solaris. The fact that it was listed in a catalog implies it was intended to be sold or at least showcased.<br />
<br />
Later on (by March 1996), the registered address was changed (from 1206 E. Arques Avenue, the site of Nvidia's first offices, to 1226 Tiros Way, its second offices) and a fax address added for someone called "Chris". This presuambly means that it was still being sold at some level by that time.</div>Starfrosthttps://nvwiki.org/index.php?title=SBus_to_VL_Converter&diff=1696SBus to VL Converter2025-12-26T23:02:47Z<p>Starfrost: </p>
<hr />
<div>The '''SBus to VL Converter''' may have been NVIDIA's first product released for sale, available by August 1995. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the [[NV1]] (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been sold by phone order or via some other non-retail channel; the product was probably intended for use on Sun Solaris. The fact that it was listed in a catalog implies it was intended to be sold or at least showcased.</div>Starfrosthttps://nvwiki.org/index.php?title=SBus_to_VL_Converter&diff=1695SBus to VL Converter2025-12-26T23:02:19Z<p>Starfrost: </p>
<hr />
<div>The '''SBus to VL Converter''' may have been NVIDIA's first product released for sale, available by August 1995. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the [[NV1]] (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been sold by phone order or via some other non-retail channel. The fact that it was listed in a catalog implies it was intended to be sold or at least showcased.</div>Starfrosthttps://nvwiki.org/index.php?title=SBus_to_VL_Converter&diff=1694SBus to VL Converter2025-12-26T23:01:48Z<p>Starfrost: </p>
<hr />
<div>The '''SBus to VL Converter''' may have been nVIDIA's first product released for sale, available by August 1995. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the [[NV1]] (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been sold by phone order or via some other non-retail channel. The fact that it was listed in a catalog implies it was intended to be sold or at least showcased.</div>Starfrosthttps://nvwiki.org/index.php?title=SBus_to_VL_Converter&diff=1693SBus to VL Converter2025-12-26T23:01:35Z<p>Starfrost: Created page with "The '''SBus to VL Converter''' may have been Nvidia's first product released for sale, available by August 1995. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the NV1 (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been..."</p>
<hr />
<div>The '''SBus to VL Converter''' may have been Nvidia's first product released for sale, available by August 1995. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the [[NV1]] (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been sold by phone order or via some other non-retail channel. The fact that it was listed in a catalog implies it was intended to be sold or at least showcased.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1690NVPlay2025-12-26T22:20:08Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| latest preview version = 1.0-rc3<br />
| latest preview date = {{Start date and age|2025|12|26|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]] and [[wikipedia:Microsoft Windows|DOS-based Microsoft Windows]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1689NVPlay2025-12-26T22:19:59Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| latest preview version = 1.0-rc3<br />
| latest preview date = {{Start date and age|2025|12|25|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]] and [[wikipedia:Microsoft Windows|DOS-based Microsoft Windows]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1688NVPlay2025-12-26T22:19:52Z<p>Starfrost: </p>
<hr />
<div>{{Infobox software<br />
| screenshot = Nvplay_6.png<br />
| caption = A screenshot of NVPlay after completing some tests on an Nvidia Riva 128<br />
| developer = [https://github.com/starfrost013/ Connor Hyde (starfrost)]<br />
| latest preview version = 1.0-rc3<br />
| latest preview date = {{Start date and age|2025|12|21|df=y}}<br />
| repo = {{URL|https://github.com/starfrost013/nvplayground/}}<br />
| operating system = [[wikipedia:MS-DOS|MS-DOS]] and [[wikipedia:Microsoft Windows|DOS-based Microsoft Windows]]<br />
| programming language = [[wikipedia:C (programming language)|C]]<br />
| genre = [[wikipedia:Device driver|Driver]], [[wikipedia:Read-eval-print loop|REPL]]<br />
| license = [[wikipedia:MIT License | MIT License]]<br />
}}<br />
<br />
'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware. <br />
<br />
By default, NVPlay runs in a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrosthttps://nvwiki.org/index.php?title=NV3&diff=1687NV32025-12-26T21:36:08Z<p>Starfrost: </p>
<hr />
<div>{{Template:Infobox GPU<br />
|title='''NV3'''<br />
|architecture=NV3<br />
|branding=RIVA 128<br />
|announcement_date=25 April 1997<br />
|release_date=25 August 1997<br />
|end_of_production=late(?) 1998<br />
|pci_vendor_id=<code>12d2</code> (SGS/Nvidia)<br />
|pci_device_id=<code>0018</code> <br />
|buses_supported=PCI, AGP 1X<br />
|directx_version=5.0<br />
|opengl_version=1.1<br />
}}<br />
<br />
The NV3 architecture is Nvidia's third-generation graphics architecture, designed from 1996 to 1997 and released at the end of August 1997<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/M_kHjM9bv8o/m/wUJnpYyJtF4J</ref> under the ''Riva 128'' branding. It was designed by a team under the direction of [[David Kirk]] and was designed to be the "fastest triangle renderer on earth" at the time while being able to be desizned in a very short time (due to Nvidia's near-bankruptcy during the period of its design), provide 2D acceleration with full, non-emulated (unlike the [[NV1]]) VGA compatibility, and at a reasonably low price. It did achieve this goal, although with many caveats: the graphics image quality was not as good as some rival cards, such as the 3dfx Voodoo, there are a few minor missing features within the architecture that were considered important at the time like trilinear texture filtering. Most importantly, the NV3 architecture was by far the fastest 2D/3D combo card, and by some measures the fastest 3D card full stop, available at the time, as 3dfx Voodoo-based cards before the Voodoo Banshee, excluding the disastrous Voodoo Rush, can only accelerate 3D applications (barring specialised "3D-on-2D" drivers), and even then only in fullscreen mode. Even when it was not used as a 3D card, it was often used as a passthrough for a 3dfx Voodoo card (despite the Riva 128 having almost equal 3D capabilities). While the Riva 128 had worse CPU scaling, performing slower on slower CPUs, despite its more complete triangle setup engine, its overall speed was slightly faster, especially on smaller triangles, albeit with somewhat worse image quality (in 1997, having a usable image at all was considered decent due to catastrophe cards like the Alliance Semiconductor aT3D, but by 1999 it was considered almost bad image quality); it could also load much larger textures (2048x2048, although impractical due to the limited VRAM, as opposed to the Voodoo's 256x256). Most NV3-architecture based graphics cards ran at a default clock speed of 100 Mhz (although some TSMC-manufactured NV3T chips are specified to run at 90 Mhz, and overclocking up to around 120 Mhz was often done safely with the requisite improvements in performance), with the pixel clock ranging up to a maximum of 230 (NV3) or 260 (NV3T) Mhz. A maximum of 4 megabytes of Video RAM is supported and the card can be run off of either the PCI 2.1 (at 66 Megahertz bus speed) or AGP 1X buses.<br />
<br />
The 2D acceleration of the NV3 architecture provides full VGA, VBE 3.0, and accelerated 2D support, Windows GDI acceleration (including full GDI ternary bitblit ROP support), point, line and rectangle drawing, image rendering, screen to screen blit with up to four manipulatable buffers (although only two are used for this purpose in practice in the Nvidia drivers), image scaling and stretching, rendering at an 8 to 32 bits per pixel colour depth at a maximum theoretical resolution of 2048*1536 and maximum practical resolution of either 1600*1200 (NV3) or 1920*1200 (NV3T), although this requires reducing the colour depth to 16bpp or lower. Other supported features of the 2D graphics pipeline include colour conversion (including RGB10, YUV420 and 422, and palette-based colour formats), colour-expansion and downconversion, color-expanded bitblit for optimised text bitmap rendering, color key, plane mask and TV-out functionality with video overlay support (via the on-board "Mediaport"). Buffers can be anywhere in VRAM with any pitch and any supported colour format. The card's VGA support is provided via a modified Weitek VGA core that Nvidia licensed.<br />
<br />
There also exists within the NV3 architecture a fairly robust (for the time), mostly Direct3D 5.0-compliant and OpenGL 1.1 3D rendering implementation. Flat shading, gouraud shading, perspective-corrected (via submission of a homogenous 1/W value to the GPU to be used for perspective correction: the GPU will not perform this itself) bilinear-filtered texture mapping, per polygon and later per-pixel (with a driver update) mip-mapping, texture interpolation and wrapping (supported texture wrapping modes are clamping, mirroring and wrapping, and they can be set separately for both the U and V coordinate), most Direct3D 5.0 rendering ROPs (additive blending from the Direct3D 5.0 specification is missing and a few others), meshes, specular highlight, a 16-bit Z-buffer (interleaved in what was called a "zeta buffer" for optimisation reasons; a stencil buffer is also emulated in software), alpha-buffering for alpha blending, hardware fog (vertex fog - applying the fog colour and intensity at a vertex level - is implemented in hardware, whereas table fog - the slightly higher quality version where the fog colour is applied at output pixel levle - is emulated using vertex fog) with 24-bit fog colour; while triangle setup (span interpolation and similar operations) are accelerated, transformation and lighting{{ref|a}} are not (this would have to wait for [[NV10]]). Most of the interface to the NV3's 3D engine is implemented via the <code>NV_D3D0Z</code> class; the interface to this class is via various methods for the control of all of the above features and then the submission of X, Y, Z, M (the aforementioned homogenous 1/W coordinte), U and V (for textures) coordinates for up to 128 triangles at a time. Although the output pixel format appears to be always 32-bit, only the 16-bit (not even 8-bit; the drivers convert any non 16-bit texture to 16-bit) <code>A4R4G4B4</code>, <code>A1R5G5B5</code>, <code>R5G5B5</code> and, via registry tweaks in the Direct3D driver, <code>R5G6B5</code> texture formats can be loaded; the largest texture size that can be loaded is 2048x2048, although in practice this is most likely done by splitting up the large texture into smaller textures, since a 2048x2048 texture (even at just 8bpp) is a minimum of 4 MB - too small to fit in the regular NV3 VRAM, and in a supported texture format will be 8 MB; too large for any variant of the NV3 architecture to support. Multitexturing is not supported; only a single texture can be supplied via the <code>NV_D3D0Z</code> class methods at a time. Up to 128 triangles can be submitted at a time, therefore it is a good idea to ensure the area covered by only one texture is close to a multiple of 128 while optimising for this graphics card.<br />
<br />
The PIO mode from the NV1 for object submission remains and is used for most basic 2D drivers, however a new DMA mode is added for faster object submission and higher three-dimensional graphics throughput.<br />
<br />
==NV3T==<br />
{{Template:Infobox GPU<br />
|title='''NV3T'''<br />
|architecture=NV3T<br />
|branding=RIVA 128 ZX<br />
|announcement_date=27 February 1998<br />
|release_date=Q2 1998<br />
|end_of_production=mid-1999<br />
|pci_vendor_id=<code>12d2</code> (SGS/Nvidia)<br />
|pci_device_id=<code>0018</code> (<code>0019</code> if ACPI is enabled)<br />
|buses_supported=PCI, AGP 2X (will run at 1X speed if 2X not supported by chipset)<br />
|directx_version=5.0<br />
|opengl_version=1.1<br />
}}<br />
<br />
The NV3T (NV3 Turbo; also known as NV3 revision C), commercialised as the ''RIVA 128 ZX'' (briefly called "RIVA 128 Turbo"), is a respin of the NV3 to allow for higher RAMDAC clock speeds (260Mhz) and more Video RAM to compete with the Intel i740. It expands the maximum amount of video RAM to 8MB, makes PFIFO's CACHE1 64 units deep instead of 32, allows for resolutions above 1600x1200 by both the aforementioned higher clocked RAMDAC in both the VGA BIOS and the drivers, and can run 3D at higher resolutions due to its higher amount of video RAM. Additionally, this was the first Nvidia GPU (other than the very few [[NV2]]'s manufactured) to be manufactured by a manufacturer that is not STMicroelectronics (then SGS-Thomson): the RIVA 128 ZX was manufactured by TSMC; it appears that they may not have had equal yields to ST (despite ST's yield crisis at the time), as some NV3Ts manufactured by TSMC are downclocked to 90 megahertz.<br />
<br />
==Tutorials==<br />
[[NV3 Getting Started]] - How to program the RIVA 128, the real way<br />
<br />
==Hardware subsystems==<br />
NV3 and NV3T share the same hardware subsystems:<br />
<br />
* [[NV3 memory mapping|Memory mapping]] - How things are mapped out<br />
* [[NV3 PMC|PMC]] - The part that controls everything else<br />
* [[NV3 rendering pipeline]] - How rendering happens<br />
** [[NV3 object submission]] - How rendering starts<br />
** [[NV3 NV_USER|NV_USER]] - How to submit objects using Programmed I/O<br />
** [[NV3 PFIFO#DMA|DMA Engine]] - How to submit objects using DMA<br />
** [[NV3 PFIFO|PFIFO]] - FIFO for optimised graphics engine submission<br />
** [[NV3 PFB|PFB]] - Framebuffer interface<br />
** [[NV3 PGRAPH|PGRAPH]] - 2D/3D graphics rendering engine (name comes from "Scene graph")<br />
** [[NV3 PGRAPH#Cache|PGRAPH_CACHE]] - Internal vertex and pixel storage<br />
** [[NV3 Graphics objects|Graphics objects]] - Available graphics objects<br />
** [[NV3 RAMIN|RAMIN]] - Where graphics objects get stored<br />
** [[NV3 RAMHT|RAMHT]] - How you find graphics objects<br />
** [[NV3 RAMFC|RAMFC]] - Where the objects go for DMA context switching<br />
** [[NV3 RAMRO|RAMRO]] - Where objects go when it all goes wrong<br />
** [[NV3 RAMAU|RAMAU]] - Remnants of what was meant to be<br />
** [[NV3 Notification Engine|Notification Engine]] - How to tell software the state of the hardware<br />
** [[NV3 PRAMDAC|PRAMDAC]] - RAMDAC for clocks, memory timings, CLUT, and sending the framebuffer to the TV or monitor<br />
* [[NV3 DPRAM|DPRAM]] - Talk to VRAM<br />
* [[NV3 PVIDEO|PVIDEO]] - Video overlay and control<br />
* [[NV3 PME|PME]] - Mediaport - Lets you plug in an external MPEG decoder<br />
* [[PRMCIO]] - CRTC for controlling a connected CRT display<br />
* [[PRMVIO]] - Legacy VGA support, courtesy of [[Weitek]]<br />
* [[PTIMER]] - Programmable interval timer<br />
* [[PDFB]] - Just a dumb framebuffer<br />
* [[RMA|Real-mode access]] - Access the GPU from real mode<br />
* [[VBIOS]] - Initialisation, POST, VGA and VESA<br />
* [[PROM]] - Read from the Video BIOS<br />
* [[PDAC]] - Optional external DAC support<br />
* [[NV3 configuration#PCI configuration registers|PCI configuration registers]] - PCI configuration registers<br />
* [[NV3 configuration#Manufacture-time configuration|Manufacture-time configuration]] - Read the manufacturer, stepping, bus size, bus and more of your GPU<br />
* [[NV3 configuration#Straps|Straps]] - OEM-level configuration<br />
<br />
==See also==<br />
* [[STG-3001]]<br />
* [[NV3 (QTM)]]<br />
<br />
==Notes==<br />
{{note|a}}The <code>NV_PGRAPH_DEBUG_2</code> register's bit 15 is officially called <code>LIGHTING_3D_ENABLED</code>, and the <code>NV_PGRAPH_STATUS</code> register's 26th bit is called <code>NV_PGRAPH_STATUS_LIGHTING</code> which can be "busy" or not. It doesn't appear that these have any real effect on how the graphics hardware behaves: they may be leftovers from [[NV2]].<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=NV1&diff=1686NV12025-12-26T21:35:15Z<p>Starfrost: </p>
<hr />
<div>{{Template:Infobox GPU<br />
|title='''NV1'''<br />
|architecture=NV1<br />
|branding=SGS-Thomson STG2000; NV1; OEM cards: Diamond Edge 3D; Jazz Multimedia 3D Magic<br />
|announcement_date=22 May 1995<br />
|release_date=Q3 1995<br />
|end_of_production=Likely between February 26, 1996 and March 3, 1996<br />
|pci_vendor_id=<code>104a</code> (SGS-Thomson; DRAM version); <code>10de</code> (NVidia; VRAM version)<br />
|pci_device_id=<code>0008</code> (main GPU)<br><code>0009</code> (VGA emulation layer)<br />
|buses_supported=VLB (never commercialised), PCI<br />
|directx_version=2.0 (badly software emulated)<br />
|opengl_version=Not supported<br />
}}<br />
<br />
TODO<br />
<br />
==Architecture reference==<br />
* [[NV1 RMC]]<br />
* [[NV1 known units]]<br />
* [[PTIMER]]<br />
* [[VBIOS]]<br />
<br />
==See also==<br />
* [[NV1 known models]]<br />
* [[NV1 known units]]<br />
<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=Template:Infobox_GPU&diff=1685Template:Infobox GPU2025-12-26T21:32:41Z<p>Starfrost: </p>
<hr />
<div><includeonly><onlyinclude><br />
{{ Infobox<br />
|autoheaders = y<br />
<br />
|title = {{{title|}}}<br />
<br />
|image = {{#if: {{{image|}}} | [[File:{{{image}}}|{{{screenshot size|290px}}}|alt={{{image alt|{{{image-caption|Screenshot}}}}}}]] }}<br />
|caption = {{{imagecaption|}}}<br />
<br />
|label1 = Branding<br />
|data1 = {{{branding|}}}<br />
<br />
<!-- Codename of the graphics hardware --><br />
|label2 = Codename<br />
|data2 = {{{codename|}}}<br />
<br />
|label3 = Architecture<br />
|data3 = {{{architecture|}}}<br />
<br />
|label4 = Era<br />
|data4 = {{{era|}}}<br />
<br />
|label5 = Announcement date<br />
|data5 = {{{announcement_date|}}}<br />
<br />
|label6 = Release date<br />
|data6 = {{{release_date|}}}<br />
<br />
|label7 = End of production<br />
|data7 = {{{end_of_production|}}}<br />
<br />
|label8 = PCI vendor ID<br />
|data8 = {{{pci_vendor_id|}}}<br />
<br />
|label9 = PCI device ID<br />
|data9 = {{{pci_device_id|}}}<br />
<br />
|label10 = <code>NV_PMC_BOOT_0</code> value<br />
|data10 = {{{pmc_boot_0|}}}<br />
<br />
|label11 = Buses supported<br />
|data11 = {{{buses|}}}<br />
<br />
|label12 = DirectX hardware supported version<br />
|data12 = {{{directx_version|}}}<br />
<br />
|label13 = OpenGL hardware supported version<br />
|data13 = {{{opengl_version|}}}<br />
<br />
<br />
<br />
}}</onlyinclude></includeonly><br />
<br />
[[Category:Templates]]</div>Starfrosthttps://nvwiki.org/index.php?title=NV3&diff=1684NV32025-12-26T21:07:43Z<p>Starfrost: </p>
<hr />
<div>{{Template:Infobox GPU<br />
|title='''NV3'''<br />
|architecture=NV3<br />
|branding=RIVA 128<br />
|announcement_date=25 April 1997<br />
|release_date=25 August 1997<br />
|end_of_production=late(?) 1998<br />
|pci_vendor_id=<code>12d2</code> (SGS/Nvidia)<br />
|pci_device_id=<code>0018</code> <br />
|buses_supported=PCI, AGP 1X<br />
|directx_version=5.0<br />
|opengl_version=1.1<br />
}}<br />
<br />
The NV3 architecture is Nvidia's third-generation graphics architecture, designed from 1996 to 1997 and released at the end of August 1997<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/M_kHjM9bv8o/m/wUJnpYyJtF4J</ref> under the ''Riva 128'' branding. It was designed by a team under the direction of [[David Kirk]] and was designed to be the "fastest triangle renderer on earth" at the time while being able to be desizned in a very short time (due to Nvidia's near-bankruptcy during the period of its design), provide 2D acceleration with full, non-emulated (unlike the [[NV1]]) VGA compatibility, and at a reasonably low price. It did achieve this goal, although with many caveats: the graphics image quality was not as good as some rival cards, such as the 3dfx Voodoo, there are a few minor missing features within the architecture that were considered important at the time like trilinear texture filtering. Most importantly, the NV3 architecture was by far the fastest 2D/3D combo card, and by some measures the fastest 3D card full stop, available at the time, as 3dfx Voodoo-based cards before the Voodoo Banshee, excluding the disastrous Voodoo Rush, can only accelerate 3D applications (barring specialised "3D-on-2D" drivers), and even then only in fullscreen mode. Even when it was not used as a 3D card, it was often used as a passthrough for a 3dfx Voodoo card (despite the Riva 128 having almost equal 3D capabilities). While the Riva 128 had worse CPU scaling, performing slower on slower CPUs, despite its more complete triangle setup engine, its overall speed was slightly faster, especially on smaller triangles, albeit with somewhat worse image quality (in 1997, having a usable image at all was considered decent due to catastrophe cards like the Alliance Semiconductor aT3D, but by 1999 it was considered almost bad image quality); it could also load much larger textures (2048x2048, although impractical due to the limited VRAM, as opposed to the Voodoo's 256x256). Most NV3-architecture based graphics cards ran at a default clock speed of 100 Mhz (although some TSMC-manufactured NV3T chips are specified to run at 90 Mhz, and overclocking up to around 120 Mhz was often done safely with the requisite improvements in performance), with the pixel clock ranging up to a maximum of 230 (NV3) or 260 (NV3T) Mhz. A maximum of 4 megabytes of Video RAM is supported and the card can be run off of either the PCI 2.1 (at 66 Megahertz bus speed) or AGP 1X buses.<br />
<br />
The 2D acceleration of the NV3 architecture provides full VGA, VBE 3.0, and accelerated 2D support, Windows GDI acceleration (including full GDI ternary bitblit ROP support), point, line and rectangle drawing, image rendering, screen to screen blit with up to four manipulatable buffers (although only two are used for this purpose in practice in the Nvidia drivers), image scaling and stretching, rendering at an 8 to 32 bits per pixel colour depth at a maximum theoretical resolution of 2048*1536 and maximum practical resolution of either 1600*1200 (NV3) or 1920*1200 (NV3T), although this requires reducing the colour depth to 16bpp or lower. Other supported features of the 2D graphics pipeline include colour conversion (including RGB10, YUV420 and 422, and palette-based colour formats), colour-expansion and downconversion, color-expanded bitblit for optimised text bitmap rendering, color key, plane mask and TV-out functionality with video overlay support (via the on-board "Mediaport"). Buffers can be anywhere in VRAM with any pitch and any supported colour format. The card's VGA support is provided via a modified Weitek VGA core that Nvidia licensed.<br />
<br />
There also exists within the NV3 architecture a fairly robust (for the time), mostly Direct3D 5.0-compliant and OpenGL 1.1 3D rendering implementation. Flat shading, gouraud shading, perspective-corrected (via submission of a homogenous 1/W value to the GPU to be used for perspective correction: the GPU will not perform this itself) bilinear-filtered texture mapping, per polygon and later per-pixel (with a driver update) mip-mapping, texture interpolation and wrapping (supported texture wrapping modes are clamping, mirroring and wrapping, and they can be set separately for both the U and V coordinate), most Direct3D 5.0 rendering ROPs (additive blending from the Direct3D 5.0 specification is missing and a few others), meshes, specular highlight, a 16-bit Z-buffer (interleaved in what was called a "zeta buffer" for optimisation reasons; a stencil buffer is also emulated in software), alpha-buffering for alpha blending, hardware fog (vertex fog - applying the fog colour and intensity at a vertex level - is implemented in hardware, whereas table fog - the slightly higher quality version where the fog colour is applied at output pixel levle - is emulated using vertex fog) with 24-bit fog colour; while triangle setup (span interpolation and similar operations) are accelerated, transformation and lighting{{ref|a}} are not (this would have to wait for [[NV10]]). Most of the interface to the NV3's 3D engine is implemented via the <code>NV_D3D0Z</code> class; the interface to this class is via various methods for the control of all of the above features and then the submission of X, Y, Z, M (the aforementioned homogenous 1/W coordinte), U and V (for textures) coordinates for up to 128 triangles at a time. Although the output pixel format appears to be always 32-bit, only the 16-bit (not even 8-bit; the drivers convert any non 16-bit texture to 16-bit) <code>A4R4G4B4</code>, <code>A1R5G5B5</code>, <code>R5G5B5</code> and, via registry tweaks in the Direct3D driver, <code>R5G6B5</code> texture formats can be loaded; the largest texture size that can be loaded is 2048x2048, although in practice this is most likely done by splitting up the large texture into smaller textures, since a 2048x2048 texture (even at just 8bpp) is a minimum of 4 MB - too small to fit in the regular NV3 VRAM, and in a supported texture format will be 8 MB; too large for any variant of the NV3 architecture to support. Multitexturing is not supported; only a single texture can be supplied via the <code>NV_D3D0Z</code> class methods at a time. Up to 128 triangles can be submitted at a time, therefore it is a good idea to ensure the area covered by only one texture is close to a multiple of 128 while optimising for this graphics card.<br />
<br />
The PIO mode from the NV1 for object submission remains and is used for most basic 2D drivers, however a new DMA mode is added for faster object submission and higher three-dimensional graphics throughput.<br />
<br />
==NV3T==<br />
{{Template:Infobox GPU<br />
|title='''NV3T'''<br />
|architecture=NV3T<br />
|branding=RIVA 128 ZX<br />
|announcement_date=27 February 1998<br />
|release_date=Q2 1998<br />
|end_of_production=mid-1999<br />
|pci_vendor_id=<code>12d2</code> (SGS/Nvidia)<br />
|pci_device_id=<code>0018</code> (<code>0019</code> if ACPI is enabled)<br />
|buses_supported=PCI, AGP 2X (will run at 1X speed if 2X not supported by chipset)<br />
|directx_version=5.0<br />
|opengl_version=1.1<br />
}}<br />
<br />
The NV3T (NV3 Turbo; also known as NV3 revision C), commercialised as the ''RIVA 128 ZX'' (briefly called "RIVA 128 Turbo"), is a respin of the NV3 to allow for higher RAMDAC clock speeds (260Mhz) and more Video RAM to compete with the Intel i740. It expands the maximum amount of video RAM to 8MB, makes PFIFO's CACHE1 64 units deep instead of 32, allows for resolutions above 1600x1200 by both the aforementioned higher clocked RAMDAC in both the VGA BIOS and the drivers, and can run 3D at higher resolutions due to its higher amount of video RAM. Additionally, this was the first Nvidia GPU (other than the very few [[NV2]]'s manfuactured) to be manufactured by a manufacturer that is not STMicroelectronics (then SGS-Thomson): the RIVA 128 ZX was manufactured by TSMC; it appears that they may not have had equal yields to ST (despite ST's yield crisis at the time), as some NV3Ts manufactured by TSMC are downclocked to 90 megahertz.<br />
<br />
==Tutorials==<br />
[[NV3 Getting Started]] - How to program the RIVA 128, the real way<br />
<br />
==Hardware subsystems==<br />
NV3 and NV3T share the same hardware subsystems:<br />
<br />
* [[NV3 memory mapping|Memory mapping]] - How things are mapped out<br />
* [[NV3 PMC|PMC]] - The part that controls everything else<br />
* [[NV3 rendering pipeline]] - How rendering happens<br />
** [[NV3 object submission]] - How rendering starts<br />
** [[NV3 NV_USER|NV_USER]] - How to submit objects using Programmed I/O<br />
** [[NV3 PFIFO#DMA|DMA Engine]] - How to submit objects using DMA<br />
** [[NV3 PFIFO|PFIFO]] - FIFO for optimised graphics engine submission<br />
** [[NV3 PFB|PFB]] - Framebuffer interface<br />
** [[NV3 PGRAPH|PGRAPH]] - 2D/3D graphics rendering engine (name comes from "Scene graph")<br />
** [[NV3 PGRAPH#Cache|PGRAPH_CACHE]] - Internal vertex and pixel storage<br />
** [[NV3 Graphics objects|Graphics objects]] - Available graphics objects<br />
** [[NV3 RAMIN|RAMIN]] - Where graphics objects get stored<br />
** [[NV3 RAMHT|RAMHT]] - How you find graphics objects<br />
** [[NV3 RAMFC|RAMFC]] - Where the objects go for DMA context switching<br />
** [[NV3 RAMRO|RAMRO]] - Where objects go when it all goes wrong<br />
** [[NV3 RAMAU|RAMAU]] - Remnants of what was meant to be<br />
** [[NV3 Notification Engine|Notification Engine]] - How to tell software the state of the hardware<br />
** [[NV3 PRAMDAC|PRAMDAC]] - RAMDAC for clocks, memory timings, CLUT, and sending the framebuffer to the TV or monitor<br />
* [[NV3 DPRAM|DPRAM]] - Talk to VRAM<br />
* [[NV3 PVIDEO|PVIDEO]] - Video overlay and control<br />
* [[NV3 PME|PME]] - Mediaport - Lets you plug in an external MPEG decoder<br />
* [[PRMCIO]] - CRTC for controlling a connected CRT display<br />
* [[PRMVIO]] - Legacy VGA support, courtesy of [[Weitek]]<br />
* [[PTIMER]] - Programmable interval timer<br />
* [[PDFB]] - Just a dumb framebuffer<br />
* [[RMA|Real-mode access]] - Access the GPU from real mode<br />
* [[VBIOS]] - Initialisation, POST, VGA and VESA<br />
* [[PROM]] - Read from the Video BIOS<br />
* [[PDAC]] - Optional external DAC support<br />
* [[NV3 configuration#PCI configuration registers|PCI configuration registers]] - PCI configuration registers<br />
* [[NV3 configuration#Manufacture-time configuration|Manufacture-time configuration]] - Read the manufacturer, stepping, bus size, bus and more of your GPU<br />
* [[NV3 configuration#Straps|Straps]] - OEM-level configuration<br />
<br />
==See also==<br />
* [[STG-3001]]<br />
* [[NV3 (QTM)]]<br />
<br />
==Notes==<br />
{{note|a}}The <code>NV_PGRAPH_DEBUG_2</code> register's bit 15 is officially called <code>LIGHTING_3D_ENABLED</code>, and the <code>NV_PGRAPH_STATUS</code> register's 26th bit is called <code>NV_PGRAPH_STATUS_LIGHTING</code> which can be "busy" or not. It doesn't appear that these have any real effect on how the graphics hardware behaves: they may be leftovers from [[NV2]].<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=Main_Page&diff=1665Main Page2025-12-26T19:56:49Z<p>Starfrost: </p>
<hr />
<div><div style="text-align:center;"><br />
= nvwiki: A wiki about Nvidia graphics cards =<br />
</div><br />
<br />
=== General ===<br />
<br />
* [[Emulation status]]<br />
* [[Hardware errata]]<br />
* [[Timeline]]<br />
<br />
=== NVPlay ===<br />
<br />
* [[NVPlay]]<br />
<br />
{{GPUs}}</div>Starfrosthttps://nvwiki.org/index.php?title=NVPlay&diff=1664NVPlay2025-12-26T19:56:45Z<p>Starfrost: Starfrost moved page NVPlay Documentation to NVPlay without leaving a redirect</p>
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<div>'''NVPlay''' is a tool designed to allow low-level communication with and control of graphics hardware, focusing on early Nvidia GPUs from the mid to late 1990s. It is a tool intended for developers to aid emulation efforts. The program will initialise your installed GPU in an entirely freestanding way without any drivers and has several modes that allow different methods to control your graphics hardware. By default it kicks you into a REPL loop that lets you run a set of commands that do register-level GPU I/O.</div>Starfrost