NvWiki - User contributions [en-gb]

SBus to VL Converter

2025-12-27T01:43:16Z

Huanker: Correct typo for "presumably"

The '''SBus to VL Converter''' may have been NVIDIA's first product released for sale, available by August 1995<ref>https://discmaster.textfiles.com/view/16967/CDware_Sep-Dec_1995.bin/.products/.wais/wais-src/Hardware_Peripherals/Interface_Devices_and_Controllers/SBUS-to-VL_Converter.html</ref>. It allowed the insertion of Sun Microsystems workstation SBus units into VESA Local Bus (a bus common on 486 and early Pentium PC motherboard machines. It was listed in a "Catalyst Catalog" in August 1995. It was likely designed for internal development work on the [[NV1]] (since many early Nvidia employees were ex-Sun Microsystems employees) and may have been sold by phone order or via some other non-retail channel; the product was probably intended for use on Sun Solaris. The fact that it was listed in a catalog implies it was intended to be sold or at least showcased.

Later on (by March 1996<ref>https://discmaster.textfiles.com/view/20246/Catalyst%20CDWARE%201996%20May%20to%20August.iso/.products/.wais/wais-src/Hardware_Peripherals/Interface_Devices_and_Controllers/SBUS-to-VL_Converter.html</ref>), the registered address was changed (from 1206 E. Arques Avenue, the site of Nvidia's first offices, to 1226 Tiros Way, its second offices) and a fax address added for someone called "Chris". This presumably means that it was still being sold at some level by that time.

NV3

2025-12-26T23:54:41Z

Huanker: Make NV3 bold + fix spelling error

{{Template:Infobox GPU
|title='''NV3'''
|architecture=NV3
|branding=RIVA 128
|announcement_date=25 April 1997
|release_date=25 August 1997
|end_of_production=late(?) 1998
|pci_vendor_id=<code>12d2</code> (SGS/Nvidia)
|pci_device_id=<code>0018</code>
|buses_supported=PCI, AGP 1X
|directx_version=5.0
|opengl_version=1.1
}}

The '''NV3''' architecture is Nvidia's third-generation graphics architecture, designed from 1996 to 1997 and released at the end of August 1997<ref>https://groups.google.com/g/comp.sys.ibm.pc.hardware.video/c/M_kHjM9bv8o/m/wUJnpYyJtF4J</ref> under the ''Riva 128'' branding. It was designed by a team under the direction of [[David Kirk]] and was designed to be the "fastest triangle renderer on earth" at the time while being able to be designed in a very short time (due to Nvidia's near-bankruptcy during the period of its design), provide 2D acceleration with full, non-emulated (unlike the [[NV1]]) VGA compatibility, and at a reasonably low price. It did achieve this goal, although with many caveats: the graphics image quality was not as good as some rival cards, such as the 3dfx Voodoo, there are a few minor missing features within the architecture that were considered important at the time like trilinear texture filtering. Most importantly, the NV3 architecture was by far the fastest 2D/3D combo card, and by some measures the fastest 3D card full stop, available at the time, as 3dfx Voodoo-based cards before the Voodoo Banshee, excluding the disastrous Voodoo Rush, can only accelerate 3D applications (barring specialised "3D-on-2D" drivers), and even then only in fullscreen mode. Even when it was not used as a 3D card, it was often used as a passthrough for a 3dfx Voodoo card (despite the Riva 128 having almost equal 3D capabilities). While the Riva 128 had worse CPU scaling, performing slower on slower CPUs, despite its more complete triangle setup engine, its overall speed was slightly faster, especially on smaller triangles, albeit with somewhat worse image quality (in 1997, having a usable image at all was considered decent due to catastrophe cards like the Alliance Semiconductor aT3D, but by 1999 it was considered almost bad image quality); it could also load much larger textures (2048x2048, although impractical due to the limited VRAM, as opposed to the Voodoo's 256x256). Most NV3-architecture based graphics cards ran at a default clock speed of 100 Mhz (although some TSMC-manufactured NV3T chips are specified to run at 90 Mhz, and overclocking up to around 120 Mhz was often done safely with the requisite improvements in performance), with the pixel clock ranging up to a maximum of 230 (NV3) or 260 (NV3T) Mhz. A maximum of 4 megabytes of Video RAM is supported and the card can be run off of either the PCI 2.1 (at 66 Megahertz bus speed) or AGP 1X buses.

The 2D acceleration of the NV3 architecture provides full VGA, VBE 3.0, and accelerated 2D support, Windows GDI acceleration (including full GDI ternary bitblit ROP support), point, line and rectangle drawing, image rendering, screen to screen blit with up to four manipulatable buffers (although only two are used for this purpose in practice in the Nvidia drivers), image scaling and stretching, rendering at an 8 to 32 bits per pixel colour depth at a maximum theoretical resolution of 2048*1536 and maximum practical resolution of either 1600*1200 (NV3) or 1920*1200 (NV3T), although this requires reducing the colour depth to 16bpp or lower. Other supported features of the 2D graphics pipeline include colour conversion (including RGB10, YUV420 and 422, and palette-based colour formats), colour-expansion and downconversion, color-expanded bitblit for optimised text bitmap rendering, color key, plane mask and TV-out functionality with video overlay support (via the on-board "Mediaport"). Buffers can be anywhere in VRAM with any pitch and any supported colour format. The card's VGA support is provided via a modified Weitek VGA core that Nvidia licensed.

There also exists within the NV3 architecture a fairly robust (for the time), mostly Direct3D 5.0-compliant and OpenGL 1.1 3D rendering implementation. Flat shading, gouraud shading, perspective-corrected (via submission of a homogenous 1/W value to the GPU to be used for perspective correction: the GPU will not perform this itself) bilinear-filtered texture mapping, per polygon and later per-pixel (with a driver update) mip-mapping, texture interpolation and wrapping (supported texture wrapping modes are clamping, mirroring and wrapping, and they can be set separately for both the U and V coordinate), most Direct3D 5.0 rendering ROPs (additive blending from the Direct3D 5.0 specification is missing and a few others), meshes, specular highlight, a 16-bit Z-buffer (interleaved in what was called a "zeta buffer" for optimisation reasons; a stencil buffer is also emulated in software), alpha-buffering for alpha blending, hardware fog (vertex fog - applying the fog colour and intensity at a vertex level - is implemented in hardware, whereas table fog - the slightly higher quality version where the fog colour is applied at output pixel levle - is emulated using vertex fog) with 24-bit fog colour; while triangle setup (span interpolation and similar operations) are accelerated, transformation and lighting{{ref|a}} are not (this would have to wait for [[NV10]]). Most of the interface to the NV3's 3D engine is implemented via the <code>NV_D3D0Z</code> class; the interface to this class is via various methods for the control of all of the above features and then the submission of X, Y, Z, M (the aforementioned homogenous 1/W coordinte), U and V (for textures) coordinates for up to 128 triangles at a time. Although the output pixel format appears to be always 32-bit, only the 16-bit (not even 8-bit; the drivers convert any non 16-bit texture to 16-bit) <code>A4R4G4B4</code>, <code>A1R5G5B5</code>, <code>R5G5B5</code> and, via registry tweaks in the Direct3D driver, <code>R5G6B5</code> texture formats can be loaded; the largest texture size that can be loaded is 2048x2048, although in practice this is most likely done by splitting up the large texture into smaller textures, since a 2048x2048 texture (even at just 8bpp) is a minimum of 4 MB - too small to fit in the regular NV3 VRAM, and in a supported texture format will be 8 MB; too large for any variant of the NV3 architecture to support. Multitexturing is not supported; only a single texture can be supplied via the <code>NV_D3D0Z</code> class methods at a time. Up to 128 triangles can be submitted at a time, therefore it is a good idea to ensure the area covered by only one texture is close to a multiple of 128 while optimising for this graphics card.

The PIO mode from the NV1 for object submission remains and is used for most basic 2D drivers, however a new DMA mode is added for faster object submission and higher three-dimensional graphics throughput.

==NV3T==
{{Template:Infobox GPU
|title='''NV3T'''
|architecture=NV3T
|branding=RIVA 128 ZX
|announcement_date=27 February 1998
|release_date=Q2 1998
|end_of_production=mid-1999
|pci_vendor_id=<code>12d2</code> (SGS/Nvidia)
|pci_device_id=<code>0018</code> (<code>0019</code> if ACPI is enabled)
|buses_supported=PCI, AGP 2X (will run at 1X speed if 2X not supported by chipset)
|directx_version=5.0
|opengl_version=1.1
}}

The NV3T (NV3 Turbo; also known as NV3 revision C), commercialised as the ''RIVA 128 ZX'' (briefly called "RIVA 128 Turbo"), is a respin of the NV3 to allow for higher RAMDAC clock speeds (260Mhz) and more Video RAM to compete with the Intel i740. It expands the maximum amount of video RAM to 8MB, makes PFIFO's CACHE1 64 units deep instead of 32, allows for resolutions above 1600x1200 by both the aforementioned higher clocked RAMDAC in both the VGA BIOS and the drivers, and can run 3D at higher resolutions due to its higher amount of video RAM. Additionally, this was the first Nvidia GPU (other than the very few [[NV2]]'s manufactured) to be manufactured by a manufacturer that is not STMicroelectronics (then SGS-Thomson): the RIVA 128 ZX was manufactured by TSMC; it appears that they may not have had equal yields to ST (despite ST's yield crisis at the time), as some NV3Ts manufactured by TSMC are downclocked to 90 megahertz.

==Tutorials==
[[NV3 Getting Started]] - How to program the RIVA 128, the real way

==Hardware subsystems==
NV3 and NV3T share the same hardware subsystems:

* [[NV3 memory mapping|Memory mapping]] - How things are mapped out
* [[NV3 PMC|PMC]] - The part that controls everything else
* [[NV3 rendering pipeline]] - How rendering happens
** [[NV3 object submission]] - How rendering starts
** [[NV3 NV_USER|NV_USER]] - How to submit objects using Programmed I/O
** [[NV3 PFIFO#DMA|DMA Engine]] - How to submit objects using DMA
** [[NV3 PFIFO|PFIFO]] - FIFO for optimised graphics engine submission
** [[NV3 PFB|PFB]] - Framebuffer interface
** [[NV3 PGRAPH|PGRAPH]] - 2D/3D graphics rendering engine (name comes from "Scene graph")
** [[NV3 PGRAPH#Cache|PGRAPH_CACHE]] - Internal vertex and pixel storage
** [[NV3 Graphics objects|Graphics objects]] - Available graphics objects
** [[NV3 RAMIN|RAMIN]] - Where graphics objects get stored
** [[NV3 RAMHT|RAMHT]] - How you find graphics objects
** [[NV3 RAMFC|RAMFC]] - Where the objects go for DMA context switching
** [[NV3 RAMRO|RAMRO]] - Where objects go when it all goes wrong
** [[NV3 RAMAU|RAMAU]] - Remnants of what was meant to be
** [[NV3 Notification Engine|Notification Engine]] - How to tell software the state of the hardware
** [[NV3 PRAMDAC|PRAMDAC]] - RAMDAC for clocks, memory timings, CLUT, and sending the framebuffer to the TV or monitor
* [[NV3 DPRAM|DPRAM]] - Talk to VRAM
* [[NV3 PVIDEO|PVIDEO]] - Video overlay and control
* [[NV3 PME|PME]] - Mediaport - Lets you plug in an external MPEG decoder
* [[PRMCIO]] - CRTC for controlling a connected CRT display
* [[PRMVIO]] - Legacy VGA support, courtesy of [[Weitek]]
* [[PTIMER]] - Programmable interval timer
* [[PDFB]] - Just a dumb framebuffer
* [[RMA|Real-mode access]] - Access the GPU from real mode
* [[VBIOS]] - Initialisation, POST, VGA and VESA
* [[PROM]] - Read from the Video BIOS
* [[PDAC]] - Optional external DAC support
* [[NV3 configuration#PCI configuration registers|PCI configuration registers]] - PCI configuration registers
* [[NV3 configuration#Manufacture-time configuration|Manufacture-time configuration]] - Read the manufacturer, stepping, bus size, bus and more of your GPU
* [[NV3 configuration#Straps|Straps]] - OEM-level configuration

==See also==
* [[STG-3001]]
* [[NV3 (QTM)]]

==Notes==
{{note|a}}The <code>NV_PGRAPH_DEBUG_2</code> register's bit 15 is officially called <code>LIGHTING_3D_ENABLED</code>, and the <code>NV_PGRAPH_STATUS</code> register's 26th bit is called <code>NV_PGRAPH_STATUS_LIGHTING</code> which can be "busy" or not. It doesn't appear that these have any real effect on how the graphics hardware behaves: they may be leftovers from [[NV2]].

{{GPUs}}

2025-12-26T17:27:33Z

Huanker: 1 revision imported

Template:Shortcut/styles.css

2025-12-26T17:26:29Z

Huanker: 1 revision imported

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border: 1px solid var(--border-color-base, #a2a9b1);
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Template:EditAtWikidata/doc

2025-12-26T17:26:29Z

Huanker: 1 revision imported

{{tsh|EAW}}
{{High-risk| 1,119,395 }}
{{Documentation subpage}}
{{Lua sidebar}}
{{Lua|Module:EditAtWikidata}}


Template to display an icon with a tooltip such as "Edit this at Wikidata".
* Icon will be linked to the Wikidata entry for the article where this is placed.
* The link can be modified to point to a specific property (or part thereof) in the Wikidata entry by supplying the optional named parameter {{para|pid}}.
* This message is only displayed if parameter {{para|1}}} is empty; i.e. when called from within a template, it can be coded not to display the icon, which means the value from Wikidata is not used.
* The Wikidata ID can optionally be supplied for testing outside the article (this is an [[WP:EXPENSIVE|expensive call]]).

== Usage ==
* <code><nowiki>{{EditAtWikidata}}</nowiki></code>

Outside the article:
* <code><nowiki>{{EditAtWikidata |qid=<Qid of article at Wikidata>}}</nowiki></code>

Inside another template:
* <code><nowiki>{{EditAtWikidata |{{{local_parameter|}}} }}</nowiki></code>

To make the link point to the given propertyID at the Wikidata entry:
* <code><nowiki>{{EditAtWikidata |pid=<PropertyID> |local_parameter}}</nowiki></code>

== Example ==


{|class="wikitable"
! !! Wikitext !! Output
|-
| With no parameters: || {{demo|br=<td>|<nowiki>{{EditAtWikidata}}</nowiki>}}
|-
| Linking to a different Wikidata item: || {{demo|br=<td>|<nowiki>{{EditAtWikidata|qid=Q42}}</nowiki>}}
|-
| Linking to a specific property in an item: || {{demo|br=<td>|<nowiki>{{EditAtWikidata|qid=Q42|pid=P735}}</nowiki>}}
|-
| Suppressing the edit link: || {{demo|br=<td>|<nowiki>{{EditAtWikidata|value}}</nowiki>}}
|}

==TemplateData==
<templatedata>
{
"params": {
"1": {
"label": "Hide the edit-at-Wikidata link?",
"description": "To prevent display of the Wikidata link. Useful for templates that add local overrides.",
"type": "boolean"
},
"qid": {
"label": "Item ID",
"description": "ID (Q-number) of the item to be edited at Wikidata.",
"example": "Q42",
"type": "string",
"default": "ID of the current page."
},
"pid": {
"label": "Property or claim ID",
"description": "ID of the property to be edited at Wikidata. Can also be a 'claim ID', to link to a particular value within a property (when there are multiple).",
"example": "P1082",
"type": "string",
"suggested": true
},
"nbsp": {
"label": "Non-breaking space",
"description": "Replaces the leading space with a non-breaking space",
"type": "boolean",
"autovalue": "yes"
}
},
"paramOrder": [
"pid",
"nbsp",
"1",
"qid"
],
"format": "inline",
"description": "Link to an item on Wikidata, with a tooltip such as \"Edit this at Wikidata\"."
}
</templatedata>

== See also ==
* [[Template:EditOnWikidata]], a similar template using text instead of an icon

<includeonly>{{sandbox other||

[[Category:Wikidata templates]]
}}</includeonly>

Template:High-risk

2025-12-26T17:26:26Z

Huanker: 1 revision imported

#REDIRECT [[Template:High-use]]

{{Rcat shell|
{{R with Wikidata item}}
{{R from merge}}
{{R from template shortcut}}
}}

Template:Tsh

2025-12-26T17:26:26Z

Huanker: 1 revision imported

#REDIRECT [[Template:Template shortcut]]

{{rcatsh|
{{R tsh}}
}}